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llvm::AArch64TargetLowering Class Reference

#include <AArch64ISelLowering.h>

+ Inheritance diagram for llvm::AArch64TargetLowering:

Public Types

enum  ConstraintType {
  C_Register, C_RegisterClass, C_Memory, C_Other,
  C_Unknown
}
 
enum  ConstraintWeight {
  CW_Invalid = -1, CW_Okay = 0, CW_Good = 1, CW_Better = 2,
  CW_Best = 3, CW_SpecificReg = CW_Okay, CW_Register = CW_Good, CW_Memory = CW_Better,
  CW_Constant = CW_Best, CW_Default = CW_Okay
}
 
typedef std::vector< ArgListEntryArgListTy
 
typedef std::vector
< AsmOperandInfo
AsmOperandInfoVector
 
enum  LegalizeAction { Legal, Promote, Expand, Custom }
 
enum  LegalizeTypeAction {
  TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat,
  TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector
}
 
enum  BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent }
 Enum that describes how the target represents true/false values. More...
 
enum  SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect }
 Enum that describes what type of support for selects the target has. More...
 
typedef std::pair
< LegalizeTypeAction, EVT
LegalizeKind
 

Public Member Functions

 AArch64TargetLowering (TargetMachine &TM)
 
CCAssignFnCCAssignFnForCall (CallingConv::ID CC, bool IsVarArg) const
 
void computeKnownBitsForTargetNode (const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
 
MVT getScalarShiftAmountTy (EVT LHSTy) const override
 
bool allowsUnalignedMemoryAccesses (EVT VT, unsigned AddrSpace=0, bool *Fast=nullptr) const override
 
SDValue LowerOperation (SDValue Op, SelectionDAG &DAG) const override
 LowerOperation - Provide custom lowering hooks for some operations. More...
 
const char * getTargetNodeName (unsigned Opcode) const override
 
SDValue PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const override
 
unsigned getFunctionAlignment (const Function *F) const
 getFunctionAlignment - Return the Log2 alignment of this function. More...
 
unsigned getMaximalGlobalOffset () const override
 
bool isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const override
 Returns true if a cast between SrcAS and DestAS is a noop. More...
 
FastISelcreateFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
 
bool isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const override
 
bool isFPImmLegal (const APFloat &Imm, EVT VT) const override
 
bool isShuffleMaskLegal (const SmallVectorImpl< int > &M, EVT VT) const override
 
EVT getSetCCResultType (LLVMContext &Context, EVT VT) const override
 getSetCCResultType - Return the ISD::SETCC ValueType More...
 
SDValue ReconstructShuffle (SDValue Op, SelectionDAG &DAG) const
 
MachineBasicBlockEmitF128CSEL (MachineInstr *MI, MachineBasicBlock *BB) const
 
MachineBasicBlockEmitInstrWithCustomInserter (MachineInstr *MI, MachineBasicBlock *MBB) const override
 
bool getTgtMemIntrinsic (IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const override
 
bool isTruncateFree (Type *Ty1, Type *Ty2) const override
 
bool isTruncateFree (EVT VT1, EVT VT2) const override
 
bool isZExtFree (Type *Ty1, Type *Ty2) const override
 
bool isZExtFree (EVT VT1, EVT VT2) const override
 
bool isZExtFree (SDValue Val, EVT VT2) const override
 
bool hasPairedLoad (Type *LoadedType, unsigned &RequiredAligment) const override
 
bool hasPairedLoad (EVT LoadedType, unsigned &RequiredAligment) const override
 
bool isLegalAddImmediate (int64_t) const override
 
bool isLegalICmpImmediate (int64_t) const override
 
EVT getOptimalMemOpType (uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
 
bool isLegalAddressingMode (const AddrMode &AM, Type *Ty) const override
 
int getScalingFactorCost (const AddrMode &AM, Type *Ty) const override
 Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value. More...
 
bool isFMAFasterThanFMulAndFAdd (EVT VT) const override
 
const MCPhysReggetScratchRegisters (CallingConv::ID CC) const override
 
bool isDesirableToCommuteWithShift (const SDNode *N) const override
 Returns false if N is a bit extraction pattern of (X >> C) & Mask. More...
 
bool shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const override
 Returns true if it is beneficial to convert a load of a constant to just the constant itself. More...
 
ValueemitLoadLinked (IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
 
ValueemitStoreConditional (IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
 
bool shouldExpandAtomicInIR (Instruction *Inst) const override
 
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction (EVT VT) const override
 
virtual unsigned getJumpTableEncoding () const
 
virtual const MCExprLowerCustomJumpTableEntry (const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
 
virtual SDValue getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const
 Returns relocation base for the given PIC jumptable. More...
 
virtual const MCExprgetPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
 
bool isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const
 
void softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const
 
std::pair< SDValue, SDValuemakeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
 Returns a pair of (return value, chain). More...
 
bool SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const
 
virtual unsigned ComputeNumSignBitsForTargetNode (SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const
 
bool isConstTrueVal (const SDNode *N) const
 
bool isConstFalseVal (const SDNode *N) const
 
SDValue SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const
 
virtual bool isGAPlusOffset (SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
 
virtual bool isTypeDesirableForOp (unsigned, EVT VT) const
 
virtual bool isDesirableToTransformToIntegerOp (unsigned, EVT) const
 
virtual bool IsDesirableToPromoteOp (SDValue, EVT &) const
 
std::pair< SDValue, SDValueLowerCallTo (CallLoweringInfo &CLI) const
 
virtual void HandleByVal (CCState *, unsigned &, unsigned) const
 Target-specific cleanup for formal ByVal parameters. More...
 
virtual const char * getClearCacheBuiltinName () const
 
virtual MVT getTypeForExtArgOrReturn (MVT VT, ISD::NodeType) const
 
virtual bool functionArgumentNeedsConsecutiveRegisters (Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
 
virtual SDValue prepareVolatileOrAtomicLoad (SDValue Chain, SDLoc DL, SelectionDAG &DAG) const
 
virtual void LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
 
bool verifyReturnAddressArgumentIsConstant (SDValue Op, SelectionDAG &DAG) const
 
virtual bool ExpandInlineAsm (CallInst *) const
 
virtual AsmOperandInfoVector ParseConstraints (ImmutableCallSite CS) const
 
virtual ConstraintWeight getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const
 
virtual void ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
 
virtual const char * LowerXConstraint (EVT ConstraintVT) const
 
SDValue BuildExactSDIV (SDValue Op1, SDValue Op2, SDLoc dl, SelectionDAG &DAG) const
 Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the constant. More...
 
SDValue BuildSDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
 Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...
 
SDValue BuildUDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
 Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...
 
bool expandMUL (SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
 
bool expandFP_TO_SINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
 
virtual void AdjustInstrPostInstrSelection (MachineInstr *MI, SDNode *Node) const
 
const TargetMachinegetTargetMachine () const
 
const DataLayoutgetDataLayout () const
 
const TargetLoweringObjectFilegetObjFileLowering () const
 
bool isBigEndian () const
 
bool isLittleEndian () const
 
virtual MVT getPointerTy (uint32_t=0) const
 
unsigned getPointerSizeInBits (uint32_t AS=0) const
 
unsigned getPointerTypeSizeInBits (Type *Ty) const
 
EVT getShiftAmountTy (EVT LHSTy) const
 
virtual MVT getVectorIdxTy () const
 
bool isSelectExpensive () const
 Return true if the select operation is expensive for this target. More...
 
virtual bool isSelectSupported (SelectSupportKind) const
 
bool hasMultipleConditionRegisters () const
 Return true if multiple condition registers are available. More...
 
bool hasExtractBitsInsn () const
 Return true if the target has BitExtract instructions. More...
 
virtual bool shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const
 
bool isIntDivCheap () const
 
bool isSlowDivBypassed () const
 Returns true if target has indicated at least one type should be bypassed. More...
 
const DenseMap< unsigned int,
unsigned int > & 
getBypassSlowDivWidths () const
 
bool isPow2DivCheap () const
 Return true if pow2 div is cheaper than a chain of srl/add/sra. More...
 
bool isJumpExpensive () const
 
bool isPredictableSelectExpensive () const
 
virtual bool isLoadBitCastBeneficial (EVT, EVT) const
 
bool isMaskAndBranchFoldingLegal () const
 Return if the target supports combining a chain like: More...
 
virtual MVT::SimpleValueType getCmpLibcallReturnType () const
 
BooleanContent getBooleanContents (bool isVec, bool isFloat) const
 
BooleanContent getBooleanContents (EVT Type) const
 
Sched::Preference getSchedulingPreference () const
 Return target scheduling preference. More...
 
virtual Sched::Preference getSchedulingPreference (SDNode *) const
 
virtual const TargetRegisterClassgetRegClassFor (MVT VT) const
 
virtual const TargetRegisterClassgetRepRegClassFor (MVT VT) const
 
virtual uint8_t getRepRegClassCostFor (MVT VT) const
 
bool isTypeLegal (EVT VT) const
 
const ValueTypeActionImplgetValueTypeActions () const
 
LegalizeTypeAction getTypeAction (LLVMContext &Context, EVT VT) const
 
LegalizeTypeAction getTypeAction (MVT VT) const
 
EVT getTypeToTransformTo (LLVMContext &Context, EVT VT) const
 
EVT getTypeToExpandTo (LLVMContext &Context, EVT VT) const
 
unsigned getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
 
virtual bool canOpTrap (unsigned Op, EVT VT) const
 
virtual bool isVectorClearMaskLegal (const SmallVectorImpl< int > &, EVT) const
 
LegalizeAction getOperationAction (unsigned Op, EVT VT) const
 
bool isOperationLegalOrCustom (unsigned Op, EVT VT) const
 
bool isOperationLegalOrPromote (unsigned Op, EVT VT) const
 
bool isOperationExpand (unsigned Op, EVT VT) const
 
bool isOperationLegal (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target. More...
 
LegalizeAction getLoadExtAction (unsigned ExtType, MVT VT) const
 
bool isLoadExtLegal (unsigned ExtType, EVT VT) const
 Return true if the specified load with extension is legal on this target. More...
 
LegalizeAction getTruncStoreAction (MVT ValVT, MVT MemVT) const
 
bool isTruncStoreLegal (EVT ValVT, EVT MemVT) const
 
LegalizeAction getIndexedLoadAction (unsigned IdxMode, MVT VT) const
 
bool isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getIndexedStoreAction (unsigned IdxMode, MVT VT) const
 
bool isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getCondCodeAction (ISD::CondCode CC, MVT VT) const
 
bool isCondCodeLegal (ISD::CondCode CC, MVT VT) const
 Return true if the specified condition code is legal on this target. More...
 
MVT getTypeToPromoteTo (unsigned Op, MVT VT) const
 
EVT getValueType (Type *Ty, bool AllowUnknown=false) const
 
MVT getSimpleValueType (Type *Ty, bool AllowUnknown=false) const
 Return the MVT corresponding to this LLVM type. See getValueType. More...
 
virtual unsigned getByValTypeAlignment (Type *Ty) const
 
MVT getRegisterType (MVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
MVT getRegisterType (LLVMContext &Context, EVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
unsigned getNumRegisters (LLVMContext &Context, EVT VT) const
 
virtual bool ShouldShrinkFPConstant (EVT) const
 
bool hasBigEndianPartOrdering (EVT VT) const
 
bool hasTargetDAGCombine (ISD::NodeType NT) const
 
unsigned getMaxStoresPerMemset (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memset. More...
 
unsigned getMaxStoresPerMemcpy (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memcpy. More...
 
unsigned getMaxStoresPerMemmove (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memmove. More...
 
virtual bool isSafeMemOpType (MVT) const
 
bool usesUnderscoreSetJmp () const
 Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More...
 
bool usesUnderscoreLongJmp () const
 Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More...
 
bool supportJumpTables () const
 Return whether the target can generate code for jump tables. More...
 
int getMinimumJumpTableEntries () const
 
unsigned getStackPointerRegisterToSaveRestore () const
 
unsigned getExceptionPointerRegister () const
 
unsigned getExceptionSelectorRegister () const
 
unsigned getJumpBufSize () const
 
unsigned getJumpBufAlignment () const
 
unsigned getMinStackArgumentAlignment () const
 Return the minimum stack alignment of an argument. More...
 
unsigned getMinFunctionAlignment () const
 Return the minimum function alignment. More...
 
unsigned getPrefFunctionAlignment () const
 Return the preferred function alignment. More...
 
unsigned getPrefLoopAlignment () const
 Return the preferred loop alignment. More...
 
bool getInsertFencesForAtomic () const
 
virtual bool getStackCookieLocation (unsigned &, unsigned &) const
 
Helpers for TargetTransformInfo implementations
int InstructionOpcodeToISD (unsigned Opcode) const
 Get the ISD node that corresponds to the Instruction class opcode. More...
 
std::pair< unsigned, MVTgetTypeLegalizationCost (Type *Ty) const
 Estimate the cost of type-legalization and the legalized type. More...
 

Static Public Member Functions

static ISD::NodeType getExtendForContent (BooleanContent Content)
 

Protected Member Functions

void initActions ()
 Initialize all of the actions to default values. More...
 

Private Member Functions

void addTypeForNEON (EVT VT, EVT PromotedBitwiseVT)
 
void addDRTypeForNEON (MVT VT)
 
void addQRTypeForNEON (MVT VT)
 
SDValue LowerFormalArguments (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
 
SDValue LowerCall (CallLoweringInfo &, SmallVectorImpl< SDValue > &InVals) const override
 
SDValue LowerCallResult (SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, bool isThisReturn, SDValue ThisVal) const
 
bool isEligibleForTailCallOptimization (SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
 
SDValue addTokenForArgument (SDValue Chain, SelectionDAG &DAG, MachineFrameInfo *MFI, int ClobberedFI) const
 
bool DoesCalleeRestoreStack (CallingConv::ID CallCC, bool TailCallOpt) const
 
bool IsTailCallConvention (CallingConv::ID CallCC) const
 
void saveVarArgRegisters (CCState &CCInfo, SelectionDAG &DAG, SDLoc DL, SDValue &Chain) const
 
bool CanLowerReturn (CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
 
SDValue LowerReturn (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc DL, SelectionDAG &DAG) const override
 
SDValue LowerGlobalAddress (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerGlobalTLSAddress (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerDarwinGlobalTLSAddress (SDValue Op, SelectionDAG &DAG) const
 Convert a TLS address reference into the correct sequence of loads and calls to compute the variable's address (for Darwin, currently) and return an SDValue containing the final node. More...
 
SDValue LowerELFGlobalTLSAddress (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerELFTLSDescCall (SDValue SymAddr, SDValue DescAddr, SDLoc DL, SelectionDAG &DAG) const
 
SDValue LowerSETCC (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerBR_CC (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerSELECT (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerSELECT_CC (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerJumpTable (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerConstantPool (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerBlockAddress (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerAAPCS_VASTART (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerDarwin_VASTART (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerVASTART (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerVACOPY (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerVAARG (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerFRAMEADDR (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerRETURNADDR (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerINSERT_VECTOR_ELT (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerEXTRACT_VECTOR_ELT (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerSCALAR_TO_VECTOR (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerBUILD_VECTOR (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerEXTRACT_SUBVECTOR (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerVectorSRA_SRL_SHL (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerShiftLeftParts (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerShiftRightParts (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerVSETCC (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerCTPOP (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerF128Call (SDValue Op, SelectionDAG &DAG, RTLIB::Libcall Call) const
 
SDValue LowerFCOPYSIGN (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerFP_EXTEND (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerFP_ROUND (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerFP_TO_INT (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerINT_TO_FP (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerVectorAND (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerVectorOR (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerCONCAT_VECTORS (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerFSINCOS (SDValue Op, SelectionDAG &DAG) const
 
ConstraintType getConstraintType (const std::string &Constraint) const override
 
unsigned getRegisterByName (const char *RegName, EVT VT) const override
 
ConstraintWeight getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const override
 
std::pair< unsigned, const
TargetRegisterClass * > 
getRegForInlineAsmConstraint (const std::string &Constraint, MVT VT) const override
 
void LowerAsmOperandForConstraint (SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
 
bool isUsedByReturnOnly (SDNode *N, SDValue &Chain) const override
 
bool mayBeEmittedAsTailCall (CallInst *CI) const override
 
bool getIndexedAddressParts (SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, bool &IsInc, SelectionDAG &DAG) const
 
bool getPreIndexedAddressParts (SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
 
bool getPostIndexedAddressParts (SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
 
void ReplaceNodeResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
 

Private Attributes

bool RequireStrictAlign
 
const AArch64SubtargetSubtarget
 

Helpers for load-linked/store-conditional atomic expansion.

virtual void resetOperationActions ()
 Reset the operation actions based on target options. More...
 
virtual bool GetAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const
 
virtual bool isVectorShiftByScalarCheap (Type *Ty) const
 
virtual bool allowTruncateForTailCall (Type *, Type *) const
 
virtual bool isFNegFree (EVT VT) const
 
virtual bool isFAbsFree (EVT VT) const
 
virtual bool isNarrowingProfitable (EVT, EVT) const
 
void setLibcallName (RTLIB::Libcall Call, const char *Name)
 Rename the default libcall routine name for the specified libcall. More...
 
const char * getLibcallName (RTLIB::Libcall Call) const
 Get the libcall routine name for the specified libcall. More...
 
void setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)
 
ISD::CondCode getCmpLibcallCC (RTLIB::Libcall Call) const
 
void setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
 Set the CallingConv that should be used for the specified libcall. More...
 
CallingConv::ID getLibcallCallingConv (RTLIB::Libcall Call) const
 Get the CallingConv that should be used for the specified libcall. More...
 
LegalizeKind getTypeConversion (LLVMContext &Context, EVT VT) const
 Reset the operation actions based on target options. More...
 
unsigned MaxStoresPerMemset
 Specify maximum number of store instructions per memset call. More...
 
unsigned MaxStoresPerMemsetOptSize
 
unsigned MaxStoresPerMemcpy
 Specify maximum bytes of store instructions per memcpy call. More...
 
unsigned MaxStoresPerMemcpyOptSize
 
unsigned MaxStoresPerMemmove
 Specify maximum bytes of store instructions per memmove call. More...
 
unsigned MaxStoresPerMemmoveOptSize
 
bool PredictableSelectIsExpensive
 
bool MaskAndBranchFoldingIsLegal
 
void setBooleanContents (BooleanContent Ty)
 
void setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy)
 
void setBooleanVectorContents (BooleanContent Ty)
 
void setSchedulingPreference (Sched::Preference Pref)
 Specify the target scheduling preference. More...
 
void setUseUnderscoreSetJmp (bool Val)
 
void setUseUnderscoreLongJmp (bool Val)
 
void setSupportJumpTables (bool Val)
 Indicate whether the target can generate code for jump tables. More...
 
void setMinimumJumpTableEntries (int Val)
 
void setStackPointerRegisterToSaveRestore (unsigned R)
 
void setExceptionPointerRegister (unsigned R)
 
void setExceptionSelectorRegister (unsigned R)
 
void setSelectIsExpensive (bool isExpensive=true)
 
void setHasMultipleConditionRegisters (bool hasManyRegs=true)
 
void setHasExtractBitsInsn (bool hasExtractInsn=true)
 
void setJumpIsExpensive (bool isExpensive=true)
 
void setIntDivIsCheap (bool isCheap=true)
 
void addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
 Tells the code generator which bitwidths to bypass. More...
 
void setPow2DivIsCheap (bool isCheap=true)
 
void addRegisterClass (MVT VT, const TargetRegisterClass *RC)
 
void clearRegisterClasses ()
 Remove all register classes. More...
 
void clearOperationActions ()
 Remove all operation actions. More...
 
virtual std::pair< const
TargetRegisterClass *, uint8_t > 
findRepresentativeClass (MVT VT) const
 
void computeRegisterProperties ()
 
void setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)
 
void setLoadExtAction (unsigned ExtType, MVT VT, LegalizeAction Action)
 
void setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)
 
void setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 
void setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 
void setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action)
 
void AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
 
void setTargetDAGCombine (ISD::NodeType NT)
 
void setJumpBufSize (unsigned Size)
 Set the target's required jmp_buf buffer size (in bytes); default is 200. More...
 
void setJumpBufAlignment (unsigned Align)
 
void setMinFunctionAlignment (unsigned Align)
 Set the target's minimum function alignment (in log2(bytes)) More...
 
void setPrefFunctionAlignment (unsigned Align)
 
void setPrefLoopAlignment (unsigned Align)
 
void setMinStackArgumentAlignment (unsigned Align)
 Set the minimum stack alignment of an argument (in log2(bytes)). More...
 
void setInsertFencesForAtomic (bool fence)
 
bool isLegalRC (const TargetRegisterClass *RC) const
 
MachineBasicBlockemitPatchPoint (MachineInstr *MI, MachineBasicBlock *MBB) const
 

Detailed Description

Definition at line 196 of file AArch64ISelLowering.h.

Member Typedef Documentation

typedef std::vector<ArgListEntry> llvm::TargetLowering::ArgListTy
inherited

Definition at line 2126 of file TargetLowering.h.

Definition at line 2484 of file TargetLowering.h.

LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.

Definition at line 106 of file TargetLowering.h.

Member Enumeration Documentation

Enum that describes how the target represents true/false values.

Enumerator
UndefinedBooleanContent 
ZeroOrOneBooleanContent 
ZeroOrNegativeOneBooleanContent 

Definition at line 109 of file TargetLowering.h.

Enumerator
C_Register 
C_RegisterClass 
C_Memory 
C_Other 
C_Unknown 

Definition at line 2425 of file TargetLowering.h.

2425  {
2426  C_Register, // Constraint represents specific register(s).
2427  C_RegisterClass, // Constraint represents any of register(s) in class.
2428  C_Memory, // Memory constraint.
2429  C_Other, // Something else.
2430  C_Unknown // Unsupported constraint.
2431  };
Enumerator
CW_Invalid 
CW_Okay 
CW_Good 
CW_Better 
CW_Best 
CW_SpecificReg 
CW_Register 
CW_Memory 
CW_Constant 
CW_Default 

Definition at line 2433 of file TargetLowering.h.

2433  {
2434  // Generic weights.
2435  CW_Invalid = -1, // No match.
2436  CW_Okay = 0, // Acceptable.
2437  CW_Good = 1, // Good weight.
2438  CW_Better = 2, // Better weight.
2439  CW_Best = 3, // Best weight.
2440 
2441  // Well-known weights.
2442  CW_SpecificReg = CW_Okay, // Specific register operands.
2443  CW_Register = CW_Good, // Register operands.
2444  CW_Memory = CW_Better, // Memory operands.
2445  CW_Constant = CW_Best, // Constant operand.
2446  CW_Default = CW_Okay // Default or don't know type.
2447  };

This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid.

Enumerator
Legal 
Promote 
Expand 
Custom 

Definition at line 84 of file TargetLowering.h.

84  {
85  Legal, // The target natively supports this operation.
86  Promote, // This operation should be executed in a larger type.
87  Expand, // Try to expand this to other ops, otherwise use a libcall.
88  Custom // Use the LowerOperation hook to implement custom lowering.
89  };

This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid.

Enumerator
TypeLegal 
TypePromoteInteger 
TypeExpandInteger 
TypeSoftenFloat 
TypeExpandFloat 
TypeScalarizeVector 
TypeSplitVector 
TypeWidenVector 

Definition at line 93 of file TargetLowering.h.

93  {
94  TypeLegal, // The target natively supports this type.
95  TypePromoteInteger, // Replace this integer with a larger one.
96  TypeExpandInteger, // Split this integer into two of half the size.
97  TypeSoftenFloat, // Convert this float to a same size integer type.
98  TypeExpandFloat, // Split this float into two of half the size.
99  TypeScalarizeVector, // Replace this one-element vector with its element.
100  TypeSplitVector, // Split this vector into two of half the size.
101  TypeWidenVector // This vector should be widened into a larger vector.
102  };

Enum that describes what type of support for selects the target has.

Enumerator
ScalarValSelect 
ScalarCondVectorVal 
VectorMaskSelect 

Definition at line 116 of file TargetLowering.h.

116  {
117  ScalarValSelect, // The target supports scalar selects (ex: cmov).
118  ScalarCondVectorVal, // The target supports selects with a scalar condition
119  // and vector values (ex: cmov).
120  VectorMaskSelect // The target supports vector selects with a vector
121  // mask (ex: x86 blends).
122  };

Constructor & Destructor Documentation

AArch64TargetLowering::AArch64TargetLowering ( TargetMachine TM)
explicit

Definition at line 77 of file AArch64ISelLowering.cpp.

80 
81  // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
82  // we have to make something up. Arbitrarily, choose ZeroOrOne.
84  // When comparing vectors the result sets the different elements in the
85  // vector to all-one or all-zero.
87 
88  // Set up the register classes.
89  addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
90  addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
91 
92  if (Subtarget->hasFPARMv8()) {
93  addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
94  addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
95  addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
96  addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
97  }
98 
99  if (Subtarget->hasNEON()) {
100  addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
101  addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
102  // Someone set us up the NEON.
109 
116  }
117 
118  // Compute derived properties from the register classes
120 
121  // Provide all sorts of operation actions
143 
147 
151 
152  // Custom lowering hooks are needed for XOR
153  // to fold it into CSINC/CSINV.
156 
157  // Virtually no operation on f128 is legal, but LLVM can't expand them when
158  // there's a valid register class, so we need custom operations in most cases.
180 
181  // Lowering for many of the conversions is actually specified by the non-f128
182  // type. The LowerXXX function will be trivial when f128 isn't involved.
197 
198  // Variable arguments.
203 
204  // Variable-sized objects.
208 
209  // Exception handling.
210  // FIXME: These are guesses. Has this been defined yet?
211  setExceptionPointerRegister(AArch64::X0);
212  setExceptionSelectorRegister(AArch64::X1);
213 
214  // Constant pool entries
216 
217  // BlockAddress
219 
220  // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
229 
230  // AArch64 lacks both left-rotate and popcount instructions.
233 
234  // AArch64 doesn't have {U|S}MUL_LOHI.
237 
238 
239  // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
240  // counterparts, which AArch64 supports directly.
245 
248 
257 
258  // Custom lower Add/Sub/Mul with overflow.
271 
280 
281  // AArch64 has implementations of a lot of rounding-like FP operations.
282  static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
283  for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
284  MVT Ty = RoundingTypes[I];
291  }
292 
294 
295  if (Subtarget->isTargetMachO()) {
296  // For iOS, we don't want to the normal expansion of a libcall to
297  // sincos. We want to issue a libcall to __sincos_stret to avoid memory
298  // traffic.
301  } else {
304  }
305 
306  // AArch64 does not have floating-point extending loads, i1 sign-extending
307  // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
320 
323 
324  // Indexed loads and stores are supported.
325  for (unsigned im = (unsigned)ISD::PRE_INC;
326  im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
339  }
340 
341  // Trap.
343 
344  // We combine OR nodes for bitfield operations.
346 
347  // Vector add and sub nodes may conceal a high-half opportunity.
348  // Also, try to fold ADD into CSINC/CSINV..
351 
355 
357 
364 
366 
369 
373 
377 
379 
381 
382  // Enable TBZ/TBNZ
384 
386 
388 
389  setHasExtractBitsInsn(true);
390 
391  if (Subtarget->hasNEON()) {
392  // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
393  // silliness like this:
419 
425 
427 
428  // AArch64 doesn't have a direct vector ->f32 conversion instructions for
429  // elements smaller than i32, so promote the input to i32 first.
434  // Similarly, there is no direct i32 -> f64 vector conversion instruction.
439 
440  // AArch64 doesn't have MUL.2d:
444  // Likewise, narrowing and extending vector loads/stores aren't handled
445  // directly.
446  for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
447  VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
448 
450  Expand);
451 
456 
458 
459  for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
460  InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
462  (MVT::SimpleValueType)InnerVT, Expand);
466  }
467 
468  // AArch64 has implementations of a lot of rounding-like FP operations.
469  static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
470  for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) {
471  MVT Ty = RoundingVecTypes[I];
478  }
479  }
480 }
void setBooleanVectorContents(BooleanContent Ty)
Same for subtraction.
Definition: ISDOpcodes.h:221
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
const AArch64Subtarget * Subtarget
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Simple binary floating point operators.
Definition: ISDOpcodes.h:227
void setTargetDAGCombine(ISD::NodeType NT)
void setBooleanContents(BooleanContent Ty)
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:622
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:317
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
void setHasExtractBitsInsn(bool hasExtractInsn=true)
void setLoadExtAction(unsigned ExtType, MVT VT, LegalizeAction Action)
TargetLowering(const TargetLowering &) LLVM_DELETED_FUNCTION
const STC & getSubtarget() const
void setExceptionPointerRegister(unsigned R)
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:314
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
void setExceptionSelectorRegister(unsigned R)
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
const StringRef getTargetTriple() const
#define I(x, y, z)
Definition: MD5.cpp:54
void setStackPointerRegisterToSaveRestore(unsigned R)
Same for multiplication.
Definition: ISDOpcodes.h:224
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:490
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
static TargetLoweringObjectFile * createTLOF(const Triple &TT)
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)

Member Function Documentation

void llvm::TargetLoweringBase::addBypassSlowDiv ( unsigned int  SlowBitWidth,
unsigned int  FastBitWidth 
)
inlineprotectedinherited

Tells the code generator which bitwidths to bypass.

Definition at line 1063 of file TargetLowering.h.

1063  {
1064  BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1065  }
DenseMap< unsigned int, unsigned int > BypassSlowDivWidths
void AArch64TargetLowering::addDRTypeForNEON ( MVT  VT)
private

Definition at line 550 of file AArch64ISelLowering.cpp.

550  {
551  addRegisterClass(VT, &AArch64::FPR64RegClass);
553 }
void addTypeForNEON(EVT VT, EVT PromotedBitwiseVT)
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
void llvm::TargetLoweringBase::AddPromotedToType ( unsigned  Opc,
MVT  OrigVT,
MVT  DestVT 
)
inlineprotectedinherited

If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. If that default is insufficient, this method can be used by the target to override the default.

Definition at line 1173 of file TargetLowering.h.

1173  {
1174  PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1175  }
std::map< std::pair< unsigned, MVT::SimpleValueType >, MVT::SimpleValueType > PromoteToType
void AArch64TargetLowering::addQRTypeForNEON ( MVT  VT)
private

Definition at line 555 of file AArch64ISelLowering.cpp.

555  {
556  addRegisterClass(VT, &AArch64::FPR128RegClass);
558 }
void addTypeForNEON(EVT VT, EVT PromotedBitwiseVT)
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
void llvm::TargetLoweringBase::addRegisterClass ( MVT  VT,
const TargetRegisterClass RC 
)
inlineprotectedinherited

Add the specified register class as an available regclass for the specified value type. This indicates the selector can handle values of that class natively.

Definition at line 1074 of file TargetLowering.h.

1074  {
1075  assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1076  AvailableRegClasses.push_back(std::make_pair(VT, RC));
1077  RegClassForVT[VT.SimpleTy] = RC;
1078  }
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
std::vector< std::pair< MVT, const TargetRegisterClass * > > AvailableRegClasses
True if this is a little endian target.
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
SDValue AArch64TargetLowering::addTokenForArgument ( SDValue  Chain,
SelectionDAG DAG,
MachineFrameInfo MFI,
int  ClobberedFI 
) const
private

Finds the incoming stack arguments which overlap the given fixed stack object and incorporates their load into the current chain. This prevents an upcoming store from clobbering the stack argument before it's used.

Definition at line 2087 of file AArch64ISelLowering.cpp.

2090  {
2091  SmallVector<SDValue, 8> ArgChains;
2092  int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2093  int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2094 
2095  // Include the original chain at the beginning of the list. When this is
2096  // used by target LowerCall hooks, this helps legalize find the
2097  // CALLSEQ_BEGIN node.
2098  ArgChains.push_back(Chain);
2099 
2100  // Add a chain value for each stack argument corresponding
2101  for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2102  UE = DAG.getEntryNode().getNode()->use_end();
2103  U != UE; ++U)
2104  if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2105  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2106  if (FI->getIndex() < 0) {
2107  int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2108  int64_t InLastByte = InFirstByte;
2109  InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2110 
2111  if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2112  (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2113  ArgChains.push_back(SDValue(L, 1));
2114  }
2115 
2116  // Build a tokenfactor for all the chains.
2117  return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2118 }
SDNode * getNode() const
get the SDNode which holds the desired result
use_iterator use_begin() const
int64_t getObjectOffset(int ObjectIdx) const
static use_iterator use_end()
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
int64_t getObjectSize(int ObjectIdx) const
void AArch64TargetLowering::addTypeForNEON ( EVT  VT,
EVT  PromotedBitwiseVT 
)
private

Definition at line 482 of file AArch64ISelLowering.cpp.

482  {
483  if (VT == MVT::v2f32) {
486 
489  } else if (VT == MVT::v2f64 || VT == MVT::v4f32) {
492 
495  }
496 
497  // Mark vector float intrinsics as expand.
498  if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
508  }
509 
522 
527 
528  // CNT supports only B element sizes.
529  if (VT != MVT::v8i8 && VT != MVT::v16i8)
531 
537 
540 
541  if (Subtarget->isLittleEndian()) {
542  for (unsigned im = (unsigned)ISD::PRE_INC;
543  im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
546  }
547  }
548 }
const AArch64Subtarget * Subtarget
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
bool isLittleEndian() const
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
void setLoadExtAction(unsigned ExtType, MVT VT, LegalizeAction Action)
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
MVT getSimpleVT() const
Definition: ValueTypes.h:204
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
void TargetLowering::AdjustInstrPostInstrSelection ( MachineInstr MI,
SDNode Node 
) const
virtualinherited

This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag. These instructions must be adjusted after instruction selection by target hooks. e.g. To fill in optional defs for ARM 's' setting instructions.

Reimplemented in llvm::ARMTargetLowering, and llvm::SITargetLowering.

Definition at line 325 of file SelectionDAGISel.cpp.

326  {
327  assert(!MI->hasPostISelHook() &&
328  "If a target marks an instruction with 'hasPostISelHook', "
329  "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
330 }
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Definition: MachineInstr.h:595
assert(Globals.size() > 1)
bool llvm::AArch64TargetLowering::allowsUnalignedMemoryAccesses ( EVT  VT,
unsigned  AddrSpace = 0,
bool *  Fast = nullptr 
) const
inlineoverridevirtual

allowsUnalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses. of the specified type.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 217 of file AArch64ISelLowering.h.

218  {
219  if (RequireStrictAlign)
220  return false;
221  // FIXME: True for Cyclone, but not necessary others.
222  if (Fast)
223  *Fast = true;
224  return true;
225  }
virtual bool llvm::TargetLoweringBase::allowTruncateForTailCall ( Type ,
Type  
) const
inlinevirtualinherited

Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail position. Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call.

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::SystemZTargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1311 of file TargetLowering.h.

1311  {
1312  return false;
1313  }
SDValue TargetLowering::BuildExactSDIV ( SDValue  Op1,
SDValue  Op2,
SDLoc  dl,
SelectionDAG DAG 
) const
inherited

Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the constant.

Definition at line 2617 of file TargetLowering.cpp.

2618  {
2619  ConstantSDNode *C = cast<ConstantSDNode>(Op2);
2620  APInt d = C->getAPIntValue();
2621  assert(d != 0 && "Division by zero!");
2622 
2623  // Shift the value upfront if it is even, so the LSB is one.
2624  unsigned ShAmt = d.countTrailingZeros();
2625  if (ShAmt) {
2626  // TODO: For UDIV use SRL instead of SRA.
2627  SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
2628  Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false,
2629  true);
2630  d = d.ashr(ShAmt);
2631  }
2632 
2633  // Calculate the multiplicative inverse, using Newton's method.
2634  APInt t, xn = d;
2635  while ((t = d*xn) != 1)
2636  xn *= APInt(d.getBitWidth(), 2) - t;
2637 
2638  Op2 = DAG.getConstant(xn, Op1.getValueType());
2639  return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2640 }
EVT getShiftAmountTy(EVT LHSTy) const
const APInt & getAPIntValue() const
int d()
assert(Globals.size() > 1)
Class for arbitrary precision integers.
Definition: APInt.h:75
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue TargetLowering::BuildSDIV ( SDNode N,
const APInt Divisor,
SelectionDAG DAG,
bool  IsAfterLegalization,
std::vector< SDNode * > *  Created 
) const
inherited

Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html

Definition at line 2646 of file TargetLowering.cpp.

2648  {
2649  EVT VT = N->getValueType(0);
2650  SDLoc dl(N);
2651 
2652  // Check to see if we can do this.
2653  // FIXME: We should be more aggressive here.
2654  if (!isTypeLegal(VT))
2655  return SDValue();
2656 
2657  APInt::ms magics = Divisor.magic();
2658 
2659  // Multiply the numerator (operand 0) by the magic value
2660  // FIXME: We should support doing a MUL in a wider type
2661  SDValue Q;
2662  if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2664  Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2665  DAG.getConstant(magics.m, VT));
2666  else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2668  Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2669  N->getOperand(0),
2670  DAG.getConstant(magics.m, VT)).getNode(), 1);
2671  else
2672  return SDValue(); // No mulhs or equvialent
2673  // If d > 0 and m < 0, add the numerator
2674  if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
2675  Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2676  if (Created)
2677  Created->push_back(Q.getNode());
2678  }
2679  // If d < 0 and m > 0, subtract the numerator.
2680  if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
2681  Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2682  if (Created)
2683  Created->push_back(Q.getNode());
2684  }
2685  // Shift right algebraic if shift value is nonzero
2686  if (magics.s > 0) {
2687  Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2688  DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2689  if (Created)
2690  Created->push_back(Q.getNode());
2691  }
2692  // Extract the sign bit and add it to the quotient
2693  SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q,
2694  DAG.getConstant(VT.getScalarSizeInBits() - 1,
2696  if (Created)
2697  Created->push_back(T.getNode());
2698  return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2699 }
unsigned s
shift amount
Definition: APInt.h:1699
const SDValue & getOperand(unsigned Num) const
ms magic() const
Definition: APInt.cpp:1396
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:320
EVT getShiftAmountTy(EVT LHSTy) const
EVT getValueType(unsigned ResNo) const
SDVTList getVTList(EVT VT)
#define T
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:240
bool isTypeLegal(EVT VT) const
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
bool isStrictlyPositive() const
Determine if this APInt Value is positive.
Definition: APInt.h:333
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Magic data for optimising signed division by a constant.
Definition: APInt.h:1697
APInt m
magic number
Definition: APInt.h:1698
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue TargetLowering::BuildUDIV ( SDNode N,
const APInt Divisor,
SelectionDAG DAG,
bool  IsAfterLegalization,
std::vector< SDNode * > *  Created 
) const
inherited

Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html

Definition at line 2705 of file TargetLowering.cpp.

2707  {
2708  EVT VT = N->getValueType(0);
2709  SDLoc dl(N);
2710 
2711  // Check to see if we can do this.
2712  // FIXME: We should be more aggressive here.
2713  if (!isTypeLegal(VT))
2714  return SDValue();
2715 
2716  // FIXME: We should use a narrower constant when the upper
2717  // bits are known to be zero.
2718  APInt::mu magics = Divisor.magicu();
2719 
2720  SDValue Q = N->getOperand(0);
2721 
2722  // If the divisor is even, we can avoid using the expensive fixup by shifting
2723  // the divided value upfront.
2724  if (magics.a != 0 && !Divisor[0]) {
2725  unsigned Shift = Divisor.countTrailingZeros();
2726  Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2727  DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
2728  if (Created)
2729  Created->push_back(Q.getNode());
2730 
2731  // Get magic number for the shifted divisor.
2732  magics = Divisor.lshr(Shift).magicu(Shift);
2733  assert(magics.a == 0 && "Should use cheap fixup now");
2734  }
2735 
2736  // Multiply the numerator (operand 0) by the magic value
2737  // FIXME: We should support doing a MUL in a wider type
2738  if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2740  Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
2741  else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2743  Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2744  DAG.getConstant(magics.m, VT)).getNode(), 1);
2745  else
2746  return SDValue(); // No mulhu or equvialent
2747  if (Created)
2748  Created->push_back(Q.getNode());
2749 
2750  if (magics.a == 0) {
2751  assert(magics.s < Divisor.getBitWidth() &&
2752  "We shouldn't generate an undefined shift!");
2753  return DAG.getNode(ISD::SRL, dl, VT, Q,
2754  DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2755  } else {
2756  SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2757  if (Created)
2758  Created->push_back(NPQ.getNode());
2759  NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2760  DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
2761  if (Created)
2762  Created->push_back(NPQ.getNode());
2763  NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2764  if (Created)
2765  Created->push_back(NPQ.getNode());
2766  return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2767  DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
2768  }
2769 }
mu magicu(unsigned LeadingZeros=0) const
Definition: APInt.cpp:1440
const SDValue & getOperand(unsigned Num) const
Magic data for optimising unsigned division by a constant.
Definition: APInt.h:1703
EVT getShiftAmountTy(EVT LHSTy) const
EVT getValueType(unsigned ResNo) const
APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.cpp:1128
SDVTList getVTList(EVT VT)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDNode * getNode() const
get the SDNode which holds the desired result
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1248
unsigned countTrailingZeros() const
Count the number of trailing zero bits.
Definition: APInt.cpp:737
APInt m
magic number
Definition: APInt.h:1704
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned s
shift amount
Definition: APInt.h:1706
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
bool a
add indicator
Definition: APInt.h:1705
bool AArch64TargetLowering::CanLowerReturn ( CallingConv::ID  CallConv,
MachineFunction MF,
bool  isVarArg,
const SmallVectorImpl< ISD::OutputArg > &  Outs,
LLVMContext Context 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 2490 of file AArch64ISelLowering.cpp.

2492  {
2494  ? RetCC_AArch64_WebKit_JS
2495  : RetCC_AArch64_AAPCS;
2497  CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
2498  return CCInfo.CheckReturn(Outs, RetCC);
2499 }
const TargetMachine & getTargetMachine() const
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
bool TargetLoweringBase::canOpTrap ( unsigned  Op,
EVT  VT 
) const
virtualinherited

Returns true if the operation can trap for the value type.

VT must be a legal type. By default, we optimistically assume most operations don't trap except for divide and remainder.

canOpTrap - Returns true if the operation can trap for the value type. VT must be a legal type.

Definition at line 869 of file TargetLoweringBase.cpp.

869  {
870  assert(isTypeLegal(VT));
871  switch (Op) {
872  default:
873  return false;
874  case ISD::FDIV:
875  case ISD::FREM:
876  case ISD::SDIV:
877  case ISD::UDIV:
878  case ISD::SREM:
879  case ISD::UREM:
880  return true;
881  }
882 }
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
CCAssignFn * AArch64TargetLowering::CCAssignFnForCall ( CallingConv::ID  CC,
bool  IsVarArg 
) const

Selects the correct CCAssignFn for a the given CallingConvention value.

Definition at line 1648 of file AArch64ISelLowering.cpp.

1649  {
1650  switch (CC) {
1651  default:
1652  llvm_unreachable("Unsupported calling convention.");
1654  return CC_AArch64_WebKit_JS;
1655  case CallingConv::C:
1656  case CallingConv::Fast:
1657  if (!Subtarget->isTargetDarwin())
1658  return CC_AArch64_AAPCS;
1659  return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
1660  }
1661 }
const AArch64Subtarget * Subtarget
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
bool isTargetDarwin() const
void llvm::TargetLoweringBase::clearOperationActions ( )
inlineprotectedinherited

Remove all operation actions.

Definition at line 1088 of file TargetLowering.h.

1088  {
1089  }
void llvm::TargetLoweringBase::clearRegisterClasses ( )
inlineprotectedinherited

Remove all register classes.

Definition at line 1081 of file TargetLowering.h.

1081  {
1082  memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1083 
1084  AvailableRegClasses.clear();
1085  }
std::vector< std::pair< MVT, const TargetRegisterClass * > > AvailableRegClasses
True if this is a little endian target.
void *memset(void *b, int c, size_t len);
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
void TargetLowering::ComputeConstraintToUse ( AsmOperandInfo OpInfo,
SDValue  Op,
SelectionDAG DAG = nullptr 
) const
virtualinherited

Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand being passed in is available, it can be passed in as Op, otherwise an empty SDValue can be passed.

ComputeConstraintToUse - Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.

Definition at line 2582 of file TargetLowering.cpp.

2584  {
2585  assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2586 
2587  // Single-letter constraints ('r') are very common.
2588  if (OpInfo.Codes.size() == 1) {
2589  OpInfo.ConstraintCode = OpInfo.Codes[0];
2590  OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2591  } else {
2592  ChooseConstraint(OpInfo, *this, Op, DAG);
2593  }
2594 
2595  // 'X' matches anything.
2596  if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2597  // Labels and constants are handled elsewhere ('X' is the only thing
2598  // that matches labels). For Functions, the type here is the type of
2599  // the result, which is not what we want to look at; leave them alone.
2600  Value *v = OpInfo.CallOperandVal;
2601  if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2602  OpInfo.CallOperandVal = v;
2603  return;
2604  }
2605 
2606  // Otherwise, try to resolve it to something we know about by looking at
2607  // the actual operand type.
2608  if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2609  OpInfo.ConstraintCode = Repl;
2610  OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2611  }
2612  }
2613 }
virtual ConstraintType getConstraintType(const std::string &Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual const char * LowerXConstraint(EVT ConstraintVT) const
assert(Globals.size() > 1)
static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, const TargetLowering &TLI, SDValue Op, SelectionDAG *DAG)
LLVM Value Representation.
Definition: Value.h:69
void AArch64TargetLowering::computeKnownBitsForTargetNode ( const SDValue  Op,
APInt KnownZero,
APInt KnownOne,
const SelectionDAG DAG,
unsigned  Depth = 0 
) const
overridevirtual

computeKnownBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

Reimplemented from llvm::TargetLowering.

Definition at line 569 of file AArch64ISelLowering.cpp.

571  {
572  switch (Op.getOpcode()) {
573  default:
574  break;
575  case AArch64ISD::CSEL: {
576  APInt KnownZero2, KnownOne2;
577  DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
578  DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
579  KnownZero &= KnownZero2;
580  KnownOne &= KnownOne2;
581  break;
582  }
583  case ISD::INTRINSIC_W_CHAIN: {
584  ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
585  Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
586  switch (IntID) {
587  default: return;
588  case Intrinsic::aarch64_ldaxr:
589  case Intrinsic::aarch64_ldxr: {
590  unsigned BitWidth = KnownOne.getBitWidth();
591  EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
592  unsigned MemBits = VT.getScalarType().getSizeInBits();
593  KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
594  return;
595  }
596  }
597  break;
598  }
600  case ISD::INTRINSIC_VOID: {
601  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
602  switch (IntNo) {
603  default:
604  break;
605  case Intrinsic::aarch64_neon_umaxv:
606  case Intrinsic::aarch64_neon_uminv: {
607  // Figure out the datatype of the vector operand. The UMINV instruction
608  // will zero extend the result, so we can mark as known zero all the
609  // bits larger than the element datatype. 32-bit or larget doesn't need
610  // this as those are legal types and will be handled by isel directly.
611  MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
612  unsigned BitWidth = KnownZero.getBitWidth();
613  if (VT == MVT::v8i8 || VT == MVT::v16i8) {
614  assert(BitWidth >= 8 && "Unexpected width!");
615  APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
616  KnownZero |= Mask;
617  } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
618  assert(BitWidth >= 16 && "Unexpected width!");
619  APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
620  KnownZero |= Mask;
621  }
622  break;
623  } break;
624  }
625  }
626  }
627 }
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
const SDValue & getOperand(unsigned Num) const
EVT getScalarType() const
Definition: ValueTypes.h:211
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1248
unsigned getOpcode() const
Class for arbitrary precision integers.
Definition: APInt.h:75
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
MVT getSimpleVT() const
Definition: ValueTypes.h:204
uint64_t getZExtValue() const
unsigned TargetLowering::ComputeNumSignBitsForTargetNode ( SDValue  Op,
const SelectionDAG DAG,
unsigned  Depth = 0 
) const
virtualinherited

This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.

ComputeNumSignBitsForTargetNode - This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.

Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 1104 of file TargetLowering.cpp.

1106  {
1110  Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1111  "Should use ComputeNumSignBits if you don't know whether Op"
1112  " is a target node!");
1113  return 1;
1114 }
assert(Globals.size() > 1)
unsigned getOpcode() const
void TargetLoweringBase::computeRegisterProperties ( )
protectedinherited

Once all of the register classes are added, this allows us to compute derived properties we expose.

computeRegisterProperties - Once all of the register classes are added, this allows us to compute derived properties we expose.

Definition at line 1025 of file TargetLoweringBase.cpp.

1025  {
1027  "Too many value types for ValueTypeActions to hold!");
1028 
1029  // Everything defaults to needing one register.
1030  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1031  NumRegistersForVT[i] = 1;
1033  }
1034  // ...except isVoid, which doesn't need any registers.
1036 
1037  // Find the largest integer register class.
1038  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1039  for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1040  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1041 
1042  // Every integer value type larger than this largest register takes twice as
1043  // many registers to represent as the previous ValueType.
1044  for (unsigned ExpandedReg = LargestIntReg + 1;
1045  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1046  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1047  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1048  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1051  }
1052 
1053  // Inspect all of the ValueType's smaller than the largest integer
1054  // register to see which ones need promotion.
1055  unsigned LegalIntReg = LargestIntReg;
1056  for (unsigned IntReg = LargestIntReg - 1;
1057  IntReg >= (unsigned)MVT::i1; --IntReg) {
1058  MVT IVT = (MVT::SimpleValueType)IntReg;
1059  if (isTypeLegal(IVT)) {
1060  LegalIntReg = IntReg;
1061  } else {
1062  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1063  (const MVT::SimpleValueType)LegalIntReg;
1065  }
1066  }
1067 
1068  // ppcf128 type is really two f64's.
1069  if (!isTypeLegal(MVT::ppcf128)) {
1074  }
1075 
1076  // Decide how to handle f128. If the target does not have native f128 support,
1077  // expand it to i128 and we will be generating soft float library calls.
1078  if (!isTypeLegal(MVT::f128)) {
1083  }
1084 
1085  // Decide how to handle f64. If the target does not have native f64 support,
1086  // expand it to i64 and we will be generating soft float library calls.
1087  if (!isTypeLegal(MVT::f64)) {
1092  }
1093 
1094  // Decide how to handle f32. If the target does not have native support for
1095  // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
1096  if (!isTypeLegal(MVT::f32)) {
1097  if (isTypeLegal(MVT::f64)) {
1102  } else {
1107  }
1108  }
1109 
1110  if (!isTypeLegal(MVT::f16)) {
1115  }
1116 
1117  // Loop over all of the vector value types to see which need transformations.
1118  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1119  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1120  MVT VT = (MVT::SimpleValueType) i;
1121  if (isTypeLegal(VT))
1122  continue;
1123 
1124  MVT EltVT = VT.getVectorElementType();
1125  unsigned NElts = VT.getVectorNumElements();
1126  bool IsLegalWiderType = false;
1127  LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1128  switch (PreferredAction) {
1129  case TypePromoteInteger: {
1130  // Try to promote the elements of integer vectors. If no legal
1131  // promotion was found, fall through to the widen-vector method.
1132  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1133  MVT SVT = (MVT::SimpleValueType) nVT;
1134  // Promote vectors of integers to vectors with the same number
1135  // of elements, with a wider element type.
1136  if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
1137  && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)
1138  && SVT.getScalarType().isInteger()) {
1139  TransformToType[i] = SVT;
1140  RegisterTypeForVT[i] = SVT;
1141  NumRegistersForVT[i] = 1;
1143  IsLegalWiderType = true;
1144  break;
1145  }
1146  }
1147  if (IsLegalWiderType)
1148  break;
1149  }
1150  case TypeWidenVector: {
1151  // Try to widen the vector.
1152  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1153  MVT SVT = (MVT::SimpleValueType) nVT;
1154  if (SVT.getVectorElementType() == EltVT
1155  && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
1156  TransformToType[i] = SVT;
1157  RegisterTypeForVT[i] = SVT;
1158  NumRegistersForVT[i] = 1;
1160  IsLegalWiderType = true;
1161  break;
1162  }
1163  }
1164  if (IsLegalWiderType)
1165  break;
1166  }
1167  case TypeSplitVector:
1168  case TypeScalarizeVector: {
1169  MVT IntermediateVT;
1170  MVT RegisterVT;
1171  unsigned NumIntermediates;
1172  NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1173  NumIntermediates, RegisterVT, this);
1174  RegisterTypeForVT[i] = RegisterVT;
1175 
1176  MVT NVT = VT.getPow2VectorType();
1177  if (NVT == VT) {
1178  // Type is already a power of 2. The default action is to split.
1180  if (PreferredAction == TypeScalarizeVector)
1182  else
1184  } else {
1185  TransformToType[i] = NVT;
1187  }
1188  break;
1189  }
1190  default:
1191  llvm_unreachable("Unknown vector legalization action!");
1192  }
1193  }
1194 
1195  // Determine the 'representative' register class for each value type.
1196  // An representative register class is the largest (meaning one which is
1197  // not a sub-register class / subreg register class) legal register class for
1198  // a group of value types. For example, on i386, i8, i16, and i32
1199  // representative would be GR32; while on x86_64 it's GR64.
1200  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1201  const TargetRegisterClass* RRC;
1202  uint8_t Cost;
1203  std::tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
1204  RepRegClassForVT[i] = RRC;
1205  RepRegClassCostForVT[i] = Cost;
1206  }
1207 }
const TargetRegisterClass * RepRegClassForVT[MVT::LAST_VALUETYPE]
MVT TransformToType[MVT::LAST_VALUETYPE]
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(MVT VT) const
unsigned getSizeInBits() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MVT getScalarType() const
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
unsigned getVectorNumElements() const
unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
ValueTypeActionImpl ValueTypeActions
True if this is a little endian target.
Y = RRC X, rotate right via carry.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
void setTypeAction(MVT VT, LegalizeTypeAction Action)
MVT getPow2VectorType() const
MVT getVectorElementType() const
uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]
FastISel * AArch64TargetLowering::createFastISel ( FunctionLoweringInfo funcInfo,
const TargetLibraryInfo libInfo 
) const
overridevirtual

createFastISel - This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.

Reimplemented from llvm::TargetLowering.

Definition at line 641 of file AArch64ISelLowering.cpp.

642  {
643  return AArch64::createFastISel(funcInfo, libInfo);
644 }
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
bool AArch64TargetLowering::DoesCalleeRestoreStack ( CallingConv::ID  CallCC,
bool  TailCallOpt 
) const
private

Definition at line 2120 of file AArch64ISelLowering.cpp.

2121  {
2122  return CallCC == CallingConv::Fast && TailCallOpt;
2123 }
MachineBasicBlock * AArch64TargetLowering::EmitF128CSEL ( MachineInstr MI,
MachineBasicBlock BB 
) const

Definition at line 763 of file AArch64ISelLowering.cpp.

764  {
765  // We materialise the F128CSEL pseudo-instruction as some control flow and a
766  // phi node:
767 
768  // OrigBB:
769  // [... previous instrs leading to comparison ...]
770  // b.ne TrueBB
771  // b EndBB
772  // TrueBB:
773  // ; Fallthrough
774  // EndBB:
775  // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
776 
778  MachineFunction *MF = MBB->getParent();
779  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
780  DebugLoc DL = MI->getDebugLoc();
781  MachineFunction::iterator It = MBB;
782  ++It;
783 
784  unsigned DestReg = MI->getOperand(0).getReg();
785  unsigned IfTrueReg = MI->getOperand(1).getReg();
786  unsigned IfFalseReg = MI->getOperand(2).getReg();
787  unsigned CondCode = MI->getOperand(3).getImm();
788  bool NZCVKilled = MI->getOperand(4).isKill();
789 
790  MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
791  MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
792  MF->insert(It, TrueBB);
793  MF->insert(It, EndBB);
794 
795  // Transfer rest of current basic-block to EndBB
796  EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
797  MBB->end());
799 
800  BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
801  BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
802  MBB->addSuccessor(TrueBB);
803  MBB->addSuccessor(EndBB);
804 
805  // TrueBB falls through to the end.
806  TrueBB->addSuccessor(EndBB);
807 
808  if (!NZCVKilled) {
809  TrueBB->addLiveIn(AArch64::NZCV);
810  EndBB->addLiveIn(AArch64::NZCV);
811  }
812 
813  BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
814  .addReg(IfTrueReg)
815  .addMBB(TrueBB)
816  .addReg(IfFalseReg)
817  .addMBB(MBB);
818 
819  MI->eraseFromParent();
820  return EndBB;
821 }
const TargetMachine & getTargetMachine() const
void addLiveIn(unsigned Reg)
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
const HexagonInstrInfo * TII
const DataLayout * DL
True if this is a little endian target.
bool isKill() const
int64_t getImm() const
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
LLVM Basic Block Representation.
Definition: BasicBlock.h:72
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
virtual const TargetInstrInfo * getInstrInfo() const
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
unsigned getReg() const
getReg - Returns the register number.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
BasicBlockListType::iterator iterator
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
MachineBasicBlock * AArch64TargetLowering::EmitInstrWithCustomInserter ( MachineInstr MI,
MachineBasicBlock MBB 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 824 of file AArch64ISelLowering.cpp.

825  {
826  switch (MI->getOpcode()) {
827  default:
828 #ifndef NDEBUG
829  MI->dump();
830 #endif
831  llvm_unreachable("Unexpected instruction for custom inserter!");
832 
833  case AArch64::F128CSEL:
834  return EmitF128CSEL(MI, BB);
835 
838  return emitPatchPoint(MI, BB);
839  }
840 }
MachineBasicBlock * EmitF128CSEL(MachineInstr *MI, MachineBasicBlock *BB) const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
int getOpcode() const
Definition: MachineInstr.h:270
MachineBasicBlock * emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const
void dump() const
Value * AArch64TargetLowering::emitLoadLinked ( IRBuilder<> &  Builder,
Value Addr,
AtomicOrdering  Ord 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 8028 of file AArch64ISelLowering.cpp.

8029  {
8030  Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8031  Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
8032  bool IsAcquire =
8033  Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent;
8034 
8035  // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
8036  // intrinsic must return {i64, i64} and we have to recombine them into a
8037  // single i128 here.
8038  if (ValTy->getPrimitiveSizeInBits() == 128) {
8039  Intrinsic::ID Int =
8040  IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
8041  Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
8042 
8043  Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8044  Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
8045 
8046  Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
8047  Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
8048  Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
8049  Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
8050  return Builder.CreateOr(
8051  Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
8052  }
8053 
8054  Type *Tys[] = { Addr->getType() };
8055  Intrinsic::ID Int =
8056  IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
8057  Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
8058 
8059  return Builder.CreateTruncOrBitCast(
8060  Builder.CreateCall(Ldxr, Addr),
8061  cast<PointerType>(Addr->getType())->getElementType());
8062 }
The main container class for the LLVM Intermediate Representation.
Definition: Module.h:115
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:118
Value * CreateExtractValue(Value *Agg, ArrayRef< unsigned > Idxs, const Twine &Name="")
Definition: IRBuilder.h:1416
Value * CreateOr(Value *LHS, Value *RHS, const Twine &Name="")
Definition: IRBuilder.h:822
Function * getDeclaration(Module *M, ID id, ArrayRef< Type * > Tys=None)
Definition: Function.cpp:737
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:278
Value * CreateZExt(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1097
Value * CreateBitCast(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1158
Type * getType() const
Definition: Value.h:215
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:77
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
Definition: Constants.cpp:528
Value * CreateTruncOrBitCast(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1182
Value * CreateShl(Value *LHS, Value *RHS, const Twine &Name="", bool HasNUW=false, bool HasNSW=false)
Definition: IRBuilder.h:751
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:336
LLVM Value Representation.
Definition: Value.h:69
CallInst * CreateCall(Value *Callee, const Twine &Name="")
Definition: IRBuilder.h:1345
LLVMContext & getContext() const
Definition: Module.h:253
MachineBasicBlock * TargetLoweringBase::emitPatchPoint ( MachineInstr MI,
MachineBasicBlock MBB 
) const
protectedinherited

Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter.

Definition at line 946 of file TargetLoweringBase.cpp.

947  {
948  MachineFunction &MF = *MI->getParent()->getParent();
949 
950  // MI changes inside this loop as we grow operands.
951  for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
952  MachineOperand &MO = MI->getOperand(OperIdx);
953  if (!MO.isFI())
954  continue;
955 
956  // foldMemoryOperand builds a new MI after replacing a single FI operand
957  // with the canonical set of five x86 addressing-mode operands.
958  int FI = MO.getIndex();
959  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
960 
961  // Copy operands before the frame-index.
962  for (unsigned i = 0; i < OperIdx; ++i)
963  MIB.addOperand(MI->getOperand(i));
964  // Add frame index operands: direct-mem-ref tag, #FI, offset.
966  MIB.addOperand(MI->getOperand(OperIdx));
967  MIB.addImm(0);
968  // Copy the operands after the frame index.
969  for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
970  MIB.addOperand(MI->getOperand(i));
971 
972  // Inherit previous memory operands.
973  MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
974  assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
975 
976  // Add a new memory operand for this FI.
977  const MachineFrameInfo &MFI = *MF.getFrameInfo();
978  assert(MFI.getObjectOffset(FI) != -1);
979  MachineMemOperand *MMO =
983  MFI.getObjectAlignment(FI));
984  MIB->addMemOperand(MF, MMO);
985 
986  // Replace the instruction and update the operand index.
987  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
988  OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
989  MI->eraseFromParent();
990  MI = MIB;
991  }
992  return MBB;
993 }
The memory access reads data.
const MachineFunction * getParent() const
const TargetMachine & TM
True if this is a little endian target.
const MCInstrDesc & getDesc() const
Definition: MachineInstr.h:266
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
bool mayLoad(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:520
Abstract Stack Frame Information.
const MachineInstrBuilder & addImm(int64_t Val) const
unsigned getNumOperands() const
Definition: MachineInstr.h:274
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:340
assert(Globals.size() > 1)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
MachineFrameInfo * getFrameInfo()
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
virtual const DataLayout * getDataLayout() const
instr_iterator insert(instr_iterator I, MachineInstr *M)
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
unsigned getPointerSize(unsigned AS=0) const
Definition: DataLayout.cpp:602
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:339
Value * AArch64TargetLowering::emitStoreConditional ( IRBuilder<> &  Builder,
Value Val,
Value Addr,
AtomicOrdering  Ord 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 8064 of file AArch64ISelLowering.cpp.

8066  {
8067  Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8068  bool IsRelease =
8069  Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent;
8070 
8071  // Since the intrinsics must have legal type, the i128 intrinsics take two
8072  // parameters: "i64, i64". We must marshal Val into the appropriate form
8073  // before the call.
8074  if (Val->getType()->getPrimitiveSizeInBits() == 128) {
8075  Intrinsic::ID Int =
8076  IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
8077  Function *Stxr = Intrinsic::getDeclaration(M, Int);
8078  Type *Int64Ty = Type::getInt64Ty(M->getContext());
8079 
8080  Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
8081  Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
8082  Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8083  return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
8084  }
8085 
8086  Intrinsic::ID Int =
8087  IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
8088  Type *Tys[] = { Addr->getType() };
8089  Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
8090 
8091  return Builder.CreateCall2(
8092  Stxr, Builder.CreateZExtOrBitCast(
8093  Val, Stxr->getFunctionType()->getParamType(0)),
8094  Addr);
8095 }
Value * CreateLShr(Value *LHS, Value *RHS, const Twine &Name="", bool isExact=false)
Definition: IRBuilder.h:770
The main container class for the LLVM Intermediate Representation.
Definition: Module.h:115
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:118
static IntegerType * getInt64Ty(LLVMContext &C)
Definition: Type.cpp:236
Function * getDeclaration(Module *M, ID id, ArrayRef< Type * > Tys=None)
Definition: Function.cpp:737
Type * getParamType(unsigned i) const
Parameter type accessors.
Definition: DerivedTypes.h:128
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:278
Value * CreateBitCast(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1158
Type * getType() const
Definition: Value.h:215
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:77
Value * CreateZExtOrBitCast(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1166
FunctionType * getFunctionType() const
Definition: Function.cpp:206
CallInst * CreateCall2(Value *Callee, Value *Arg1, Value *Arg2, const Twine &Name="")
Definition: IRBuilder.h:1351
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:336
Value * CreateTrunc(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1094
LLVM Value Representation.
Definition: Value.h:69
LLVMContext & getContext() const
Definition: Module.h:253
CallInst * CreateCall3(Value *Callee, Value *Arg1, Value *Arg2, Value *Arg3, const Twine &Name="")
Definition: IRBuilder.h:1356
bool TargetLowering::expandFP_TO_SINT ( SDNode N,
SDValue Result,
SelectionDAG DAG 
) const
inherited

Expand float(f32) to SINT(i64) conversion

Parameters
NNode to expand
Resultoutput after conversion
Returns
True, if the expansion was successful, false otherwise

Definition at line 2889 of file TargetLowering.cpp.

2890  {
2891  EVT VT = Node->getOperand(0).getValueType();
2892  EVT NVT = Node->getValueType(0);
2893  SDLoc dl(SDValue(Node, 0));
2894 
2895  // FIXME: Only f32 to i64 conversions are supported.
2896  if (VT != MVT::f32 || NVT != MVT::i64)
2897  return false;
2898 
2899  // Expand f32 -> i64 conversion
2900  // This algorithm comes from compiler-rt's implementation of fixsfdi:
2901  // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
2902  EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
2903  VT.getSizeInBits());
2904  SDValue ExponentMask = DAG.getConstant(0x7F800000, IntVT);
2905  SDValue ExponentLoBit = DAG.getConstant(23, IntVT);
2906  SDValue Bias = DAG.getConstant(127, IntVT);
2907  SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()),
2908  IntVT);
2909  SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT);
2910  SDValue MantissaMask = DAG.getConstant(0x007FFFFF, IntVT);
2911 
2912  SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
2913 
2914  SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT,
2915  DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
2916  DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT)));
2917  SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
2918 
2919  SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
2920  DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
2921  DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT)));
2922  Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
2923 
2924  SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
2925  DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
2926  DAG.getConstant(0x00800000, IntVT));
2927 
2928  R = DAG.getZExtOrTrunc(R, dl, NVT);
2929 
2930 
2931  R = DAG.getSelectCC(dl, Exponent, ExponentLoBit,
2932  DAG.getNode(ISD::SHL, dl, NVT, R,
2933  DAG.getZExtOrTrunc(
2934  DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
2935  dl, getShiftAmountTy(IntVT))),
2936  DAG.getNode(ISD::SRL, dl, NVT, R,
2937  DAG.getZExtOrTrunc(
2938  DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
2939  dl, getShiftAmountTy(IntVT))),
2940  ISD::SETGT);
2941 
2942  SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
2943  DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
2944  Sign);
2945 
2946  Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, IntVT),
2947  DAG.getConstant(0, NVT), Ret, ISD::SETLT);
2948  return true;
2949 }
static APInt getSignBit(unsigned BitWidth)
Get the SignBit for a specific bit width.
Definition: APInt.h:441
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
SDValue getSelectCC(SDLoc DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Definition: SelectionDAG.h:716
EVT getShiftAmountTy(EVT LHSTy) const
const DomTreeNodeT * Node
SDValue getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Definition: ValueTypes.h:62
virtual bool llvm::TargetLowering::ExpandInlineAsm ( CallInst ) const
inlinevirtualinherited

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. This is useful for turning simple inline asms into LLVM intrinsics, which gives the compiler more information about the behavior of the code.

Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.

Definition at line 2421 of file TargetLowering.h.

2421  {
2422  return false;
2423  }
bool TargetLowering::expandMUL ( SDNode N,
SDValue Lo,
SDValue Hi,
EVT  HiLoVT,
SelectionDAG DAG,
SDValue  LL = SDValue(),
SDValue  LH = SDValue(),
SDValue  RL = SDValue(),
SDValue  RH = SDValue() 
) const
inherited

Expand a MUL into two nodes. One that computes the high bits of the result and one that computes the low bits.

Parameters
HiLoVTThe value type to use for the Lo and Hi nodes.
LLLow bits of the LHS of the MUL. You can use this parameter if you want to control how low bits are extracted from the LHS.
LHHigh bits of the LHS of the MUL. See LL for meaning.
RLLow bits of the RHS of the MUL. See LL for meaning
RHHigh bits of the RHS of the MUL. See LL for meaning.
Returns
true if the node has been expanded. false if it has not

Definition at line 2786 of file TargetLowering.cpp.

2788  {
2789  EVT VT = N->getValueType(0);
2790  SDLoc dl(N);
2791 
2792  bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
2793  bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
2794  bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
2795  bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
2796  if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
2797  unsigned OuterBitSize = VT.getSizeInBits();
2798  unsigned InnerBitSize = HiLoVT.getSizeInBits();
2799  unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
2800  unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
2801 
2802  // LL, LH, RL, and RH must be either all NULL or all set to a value.
2803  assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
2804  (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
2805 
2806  if (!LL.getNode() && !RL.getNode() &&
2808  LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0));
2809  RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
2810  }
2811 
2812  if (!LL.getNode())
2813  return false;
2814 
2815  APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
2816  if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
2817  DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
2818  // The inputs are both zero-extended.
2819  if (HasUMUL_LOHI) {
2820  // We can emit a umul_lohi.
2821  Lo = DAG.getNode(ISD::UMUL_LOHI, dl,
2822  DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2823  Hi = SDValue(Lo.getNode(), 1);
2824  return true;
2825  }
2826  if (HasMULHU) {
2827  // We can emit a mulhu+mul.
2828  Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2829  Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2830  return true;
2831  }
2832  }
2833  if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
2834  // The input values are both sign-extended.
2835  if (HasSMUL_LOHI) {
2836  // We can emit a smul_lohi.
2837  Lo = DAG.getNode(ISD::SMUL_LOHI, dl,
2838  DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2839  Hi = SDValue(Lo.getNode(), 1);
2840  return true;
2841  }
2842  if (HasMULHS) {
2843  // We can emit a mulhs+mul.
2844  Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2845  Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL);
2846  return true;
2847  }
2848  }
2849 
2850  if (!LH.getNode() && !RH.getNode() &&
2853  unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits();
2854  SDValue Shift = DAG.getConstant(ShiftAmt, getShiftAmountTy(VT));
2855  LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
2856  LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
2857  RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
2858  RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
2859  }
2860 
2861  if (!LH.getNode())
2862  return false;
2863 
2864  if (HasUMUL_LOHI) {
2865  // Lo,Hi = umul LHS, RHS.
2866  SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
2867  DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2868  Lo = UMulLOHI;
2869  Hi = UMulLOHI.getValue(1);
2870  RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2871  LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2872  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2873  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2874  return true;
2875  }
2876  if (HasMULHU) {
2877  Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2878  Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2879  RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2880  LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2881  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2882  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2883  return true;
2884  }
2885  }
2886  return false;
2887 }
SDValue getValue(unsigned R) const
const SDValue & getOperand(unsigned Num) const
EVT getShiftAmountTy(EVT LHSTy) const
EVT getValueType(unsigned ResNo) const
SDVTList getVTList(EVT VT)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Class for arbitrary precision integers.
Definition: APInt.h:75
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
std::pair< const TargetRegisterClass *, uint8_t > TargetLoweringBase::findRepresentativeClass ( MVT  VT) const
protectedvirtualinherited

Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

findRepresentativeClass - Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.

Definition at line 998 of file TargetLoweringBase.cpp.

998  {
1000  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1001  if (!RC)
1002  return std::make_pair(RC, 0);
1003 
1004  // Compute the set of all super-register classes.
1005  BitVector SuperRegRC(TRI->getNumRegClasses());
1006  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1007  SuperRegRC.setBitsInMask(RCI.getMask());
1008 
1009  // Find the first legal register class with the largest spill size.
1010  const TargetRegisterClass *BestRC = RC;
1011  for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
1012  const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1013  // We want the largest possible spill size.
1014  if (SuperRC->getSize() <= BestRC->getSize())
1015  continue;
1016  if (!isLegalRC(SuperRC))
1017  continue;
1018  BestRC = SuperRC;
1019  }
1020  return std::make_pair(BestRC, 1);
1021 }
const TargetMachine & getTargetMachine() const
unsigned getNumRegClasses() const
const TargetRegisterClass * getRegClass(unsigned i) const
SimpleValueType SimpleTy
bool isLegalRC(const TargetRegisterClass *RC) const
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
virtual const TargetRegisterInfo * getRegisterInfo() const
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
Definition: BitVector.h:496
virtual bool llvm::TargetLowering::functionArgumentNeedsConsecutiveRegisters ( Type Ty,
CallingConv::ID  CallConv,
bool  isVarArg 
) const
inlinevirtualinherited

For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.

Reimplemented in llvm::PPCTargetLowering, and llvm::ARMTargetLowering.

Definition at line 2337 of file TargetLowering.h.

2338  {
2339  return false;
2340  }
virtual bool llvm::TargetLoweringBase::GetAddrModeArguments ( IntrinsicInst ,
SmallVectorImpl< Value * > &  ,
Type *&   
) const
inlinevirtualinherited

CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. This allows as much computation as possible to be done in the address mode for that operand. This hook lets targets also pass back when this should be done on intrinsics which load/store.

Definition at line 1236 of file TargetLowering.h.

1238  {
1239  return false;
1240  }
BooleanContent llvm::TargetLoweringBase::getBooleanContents ( bool  isVec,
bool  isFloat 
) const
inlineinherited

For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1.

"Boolean values" are special true/false values produced by nodes like SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. Not to be confused with general values promoted from i1. Some cpus distinguish between vectors of boolean and scalars; the isVec parameter selects between the two kinds. For example on X86 a scalar boolean should be zero extended from i1, while the elements of a vector of booleans should be sign extended from i1.

Some cpus also treat floating point types the same way as they treat vectors instead of the way they treat scalars.

Definition at line 290 of file TargetLowering.h.

290  {
291  if (isVec)
292  return BooleanVectorContents;
293  return isFloat ? BooleanFloatContents : BooleanContents;
294  }
BooleanContent BooleanVectorContents
BooleanContent BooleanFloatContents
BooleanContent BooleanContents
BooleanContent llvm::TargetLoweringBase::getBooleanContents ( EVT  Type) const
inlineinherited

Definition at line 296 of file TargetLowering.h.

296  {
297  return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
298  }
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
RelocType Type
Definition: COFFYAML.cpp:285
const DenseMap<unsigned int, unsigned int>& llvm::TargetLoweringBase::getBypassSlowDivWidths ( ) const
inlineinherited

Returns map of slow types for division or remainder with corresponding fast types

Definition at line 222 of file TargetLowering.h.

222  {
223  return BypassSlowDivWidths;
224  }
DenseMap< unsigned int, unsigned int > BypassSlowDivWidths
unsigned TargetLoweringBase::getByValTypeAlignment ( Type Ty) const
virtualinherited

Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area. This is the actual alignment, not its logarithm.

getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area. This is the actual alignment, not its logarithm.

Reimplemented in llvm::X86TargetLowering, and llvm::PPCTargetLowering.

Definition at line 1345 of file TargetLoweringBase.cpp.

1345  {
1346  return DL->getABITypeAlignment(Ty);
1347 }
const DataLayout * DL
True if this is a little endian target.
unsigned getABITypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:683
virtual const char* llvm::TargetLowering::getClearCacheBuiltinName ( ) const
inlinevirtualinherited

Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cache library call

Reimplemented in llvm::X86TargetLowering.

Definition at line 2310 of file TargetLowering.h.

2310  {
2311  return "__clear_cache";
2312  }
ISD::CondCode llvm::TargetLoweringBase::getCmpLibcallCC ( RTLIB::Libcall  Call) const
inlineinherited

Get the CondCode that's to be used to test the result of the comparison libcall against zero.

Definition at line 1437 of file TargetLowering.h.

1437  {
1438  return CmpLibcallCCs[Call];
1439  }
ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]
MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType ( ) const
virtualinherited

Return the ValueType for comparison libcalls. Comparions libcalls include floating point comparion calls, and Ordered/Unordered check calls on floating point numbers.

Definition at line 1214 of file TargetLoweringBase.cpp.

1214  {
1215  return MVT::i32; // return the default value
1216 }
LegalizeAction llvm::TargetLoweringBase::getCondCodeAction ( ISD::CondCode  CC,
MVT  VT 
) const
inlineinherited

Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 589 of file TargetLowering.h.

589  {
590  assert((unsigned)CC < array_lengthof(CondCodeActions) &&
591  ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
592  "Table isn't big enough!");
593  // See setCondCodeAction for how this is encoded.
594  uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
595  uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
596  LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
597  assert(Action != Promote && "Can't promote condition code!");
598  return Action;
599  }
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
static int Value(bit_value_t V)
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE+15)/16]
AArch64TargetLowering::ConstraintType AArch64TargetLowering::getConstraintType ( const std::string &  Constraint) const
overrideprivatevirtual

getConstraintType - Given a constraint letter, return the type of constraint it is for this target.

Reimplemented from llvm::TargetLowering.

Definition at line 3857 of file AArch64ISelLowering.cpp.

3857  {
3858  if (Constraint.size() == 1) {
3859  switch (Constraint[0]) {
3860  default:
3861  break;
3862  case 'z':
3863  return C_Other;
3864  case 'x':
3865  case 'w':
3866  return C_RegisterClass;
3867  // An address with a single base register. Due to the way we
3868  // currently handle addresses it is the same as 'r'.
3869  case 'Q':
3870  return C_Memory;
3871  }
3872  }
3873  return TargetLowering::getConstraintType(Constraint);
3874 }
virtual ConstraintType getConstraintType(const std::string &Constraint) const
Given a constraint, return the type of constraint it is for this target.
const DataLayout* llvm::TargetLoweringBase::getDataLayout ( ) const
inlineinherited

Definition at line 150 of file TargetLowering.h.

150 { return DL; }
const DataLayout * DL
True if this is a little endian target.
unsigned llvm::TargetLoweringBase::getExceptionPointerRegister ( ) const
inlineinherited

If a physical register, this returns the register that receives the exception address on entry to a landing pad.

Definition at line 845 of file TargetLowering.h.

845  {
847  }
unsigned llvm::TargetLoweringBase::getExceptionSelectorRegister ( ) const
inlineinherited

If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.

Definition at line 851 of file TargetLowering.h.

851  {
853  }
static ISD::NodeType llvm::TargetLoweringBase::getExtendForContent ( BooleanContent  Content)
inlinestaticinherited

Definition at line 124 of file TargetLowering.h.

124  {
125  switch (Content) {
127  // Extend by adding rubbish bits.
128  return ISD::ANY_EXTEND;
130  // Extend by adding zero bits.
131  return ISD::ZERO_EXTEND;
133  // Extend by copying the sign bit.
134  return ISD::SIGN_EXTEND;
135  }
136  llvm_unreachable("Invalid content kind");
137  }
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
unsigned AArch64TargetLowering::getFunctionAlignment ( const Function F) const

getFunctionAlignment - Return the Log2 alignment of this function.

Definition at line 1636 of file AArch64ISelLowering.cpp.

1636  {
1637  return 2;
1638 }
bool AArch64TargetLowering::getIndexedAddressParts ( SDNode Op,
SDValue Base,
SDValue Offset,
ISD::MemIndexedMode AM,
bool &  IsInc,
SelectionDAG DAG 
) const
private

Definition at line 7900 of file AArch64ISelLowering.cpp.

7904  {
7905  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
7906  return false;
7907 
7908  Base = Op->getOperand(0);
7909  // All of the indexed addressing mode instructions take a signed
7910  // 9 bit immediate offset.
7911  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
7912  int64_t RHSC = (int64_t)RHS->getZExtValue();
7913  if (RHSC >= 256 || RHSC <= -256)
7914  return false;
7915  IsInc = (Op->getOpcode() == ISD::ADD);
7916  Offset = Op->getOperand(1);
7917  return true;
7918  }
7919  return false;
7920 }
unsigned getOpcode() const
const SDValue & getOperand(unsigned Num) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
LegalizeAction llvm::TargetLoweringBase::getIndexedLoadAction ( unsigned  IdxMode,
MVT  VT 
) const
inlineinherited

Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 553 of file TargetLowering.h.

553  {
555  "Table isn't big enough!");
556  unsigned Ty = (unsigned)VT.SimpleTy;
557  return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
558  }
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
assert(Globals.size() > 1)
LegalizeAction llvm::TargetLoweringBase::getIndexedStoreAction ( unsigned  IdxMode,
MVT  VT 
) const
inlineinherited

Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 571 of file TargetLowering.h.

571  {
573  "Table isn't big enough!");
574  unsigned Ty = (unsigned)VT.SimpleTy;
575  return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
576  }
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
assert(Globals.size() > 1)
bool llvm::TargetLoweringBase::getInsertFencesForAtomic ( ) const
inlineinherited

Return whether the DAG builder should automatically insert fences and reduce ordering for atomics.

Definition at line 889 of file TargetLowering.h.

889  {
890  return InsertFencesForAtomic;
891  }
unsigned llvm::TargetLoweringBase::getJumpBufAlignment ( ) const
inlineinherited

Returns the target's jmp_buf alignment in bytes (if never set, the default is 0)

Definition at line 863 of file TargetLowering.h.

863  {
864  return JumpBufAlignment;
865  }
unsigned JumpBufAlignment
The alignment, in bytes, of the target's jmp_buf buffers.
unsigned llvm::TargetLoweringBase::getJumpBufSize ( ) const
inlineinherited

Returns the target's jmp_buf size in bytes (if never set, the default is 200)

Definition at line 857 of file TargetLowering.h.

857  {
858  return JumpBufSize;
859  }
unsigned JumpBufSize
The size, in bytes, of the target's jmp_buf buffers.
unsigned TargetLowering::getJumpTableEncoding ( ) const
virtualinherited

Return the entry encoding for a jump table in the current function. The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.

getJumpTableEncoding - Return the entry encoding for a jump table in the current function. The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.

Reimplemented in llvm::MipsTargetLowering, llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::XCoreTargetLowering.

Definition at line 222 of file TargetLowering.cpp.

222  {
223  // In non-pic modes, just use the address of a block.
224  if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
226 
227  // In PIC mode, if the target supports a GPRel32 directive, use it.
228  if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
230 
231  // Otherwise, use a label difference.
233 }
const TargetMachine & getTargetMachine() const
CallingConv::ID llvm::TargetLoweringBase::getLibcallCallingConv ( RTLIB::Libcall  Call) const
inlineinherited

Get the CallingConv that should be used for the specified libcall.

Definition at line 1447 of file TargetLowering.h.

1447  {
1448  return LibcallCallingConvs[Call];
1449  }
CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]
Stores the CallingConv that should be used for each libcall.
const char* llvm::TargetLoweringBase::getLibcallName ( RTLIB::Libcall  Call) const
inlineinherited

Get the libcall routine name for the specified libcall.

Definition at line 1425 of file TargetLowering.h.

1425  {
1426  return LibcallRoutineNames[Call];
1427  }
const char * LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]
Stores the name each libcall.
LegalizeAction llvm::TargetLoweringBase::getLoadExtAction ( unsigned  ExtType,
MVT  VT 
) const
inlineinherited

Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 520 of file TargetLowering.h.

520  {
522  "Table isn't big enough!");
523  return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType];
524  }
assert(Globals.size() > 1)
uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]
unsigned AArch64TargetLowering::getMaximalGlobalOffset ( ) const
overridevirtual

getMaximalGlobalOffset - Returns the maximal possible offset which can be used for loads / stores from the global.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 633 of file AArch64ISelLowering.cpp.

633  {
634  // FIXME: On AArch64, this depends on the type.
635  // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
636  // and the offset has to be a multiple of the related size in bytes.
637  return 4095;
638 }
unsigned llvm::TargetLoweringBase::getMaxStoresPerMemcpy ( bool  OptSize) const
inlineinherited

Get maximum # of store operations permitted for llvm.memcpy.

This function returns the maximum number of store operations permitted to replace a call to llvm.memcpy. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 758 of file TargetLowering.h.

758  {
760  }
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
unsigned llvm::TargetLoweringBase::getMaxStoresPerMemmove ( bool  OptSize) const
inlineinherited

Get maximum # of store operations permitted for llvm.memmove.

This function returns the maximum number of store operations permitted to replace a call to llvm.memmove. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 768 of file TargetLowering.h.

768  {
770  }
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
unsigned llvm::TargetLoweringBase::getMaxStoresPerMemset ( bool  OptSize) const
inlineinherited

Get maximum # of store operations permitted for llvm.memset.

This function returns the maximum number of store operations permitted to replace a call to llvm.memset. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 748 of file TargetLowering.h.

748  {
750  }
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned llvm::TargetLoweringBase::getMinFunctionAlignment ( ) const
inlineinherited

Return the minimum function alignment.

Definition at line 873 of file TargetLowering.h.

873  {
874  return MinFunctionAlignment;
875  }
int llvm::TargetLoweringBase::getMinimumJumpTableEntries ( ) const
inlineinherited

Return integer threshold on number of blocks to use jump tables rather than if sequence.

Definition at line 833 of file TargetLowering.h.

833  {
835  }
int MinimumJumpTableEntries
Number of blocks threshold to use jump tables.
unsigned llvm::TargetLoweringBase::getMinStackArgumentAlignment ( ) const
inlineinherited

Return the minimum stack alignment of an argument.

Definition at line 868 of file TargetLowering.h.

868  {
870  }
unsigned MinStackArgumentAlignment
The minimum alignment that any argument on the stack needs to have.
TargetLowering::ConstraintWeight TargetLowering::getMultipleConstraintMatchWeight ( AsmOperandInfo info,
int  maIndex 
) const
virtualinherited

Examine constraint type and operand type and determine a weight value. The operand object must already have been set up with the operand type.

Examine constraint type and operand type and determine a weight value. This object must already have been set up with the operand type and the current alternative constraint selected.

Definition at line 2442 of file TargetLowering.cpp.

2443  {
2445  if (maIndex >= (int)info.multipleAlternatives.size())
2446  rCodes = &info.Codes;
2447  else
2448  rCodes = &info.multipleAlternatives[maIndex].Codes;
2449  ConstraintWeight BestWeight = CW_Invalid;
2450 
2451  // Loop over the options, keeping track of the most general one.
2452  for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2453  ConstraintWeight weight =
2454  getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2455  if (weight > BestWeight)
2456  BestWeight = weight;
2457  }
2458 
2459  return BestWeight;
2460 }
lazy value info
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
std::vector< std::string > ConstraintCodeVector
Definition: InlineAsm.h:102
SmallVectorImpl< T >::const_pointer c_str(SmallVectorImpl< T > &str)
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
unsigned llvm::TargetLoweringBase::getNumRegisters ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

Return the number of registers that this ValueType will eventually require.

This is one for any types promoted to live in larger registers, but may be more than one for types (like i64) that are split into pieces. For types like i140, which are first promoted then expanded, it is the number of registers needed to hold all the bits of the original type. For an i140 on a 32 bit machine this means 5 registers.

Definition at line 703 of file TargetLowering.h.

703  {
704  if (VT.isSimple()) {
705  assert((unsigned)VT.getSimpleVT().SimpleTy <
707  return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
708  }
709  if (VT.isVector()) {
710  EVT VT1;
711  MVT VT2;
712  unsigned NumIntermediates;
713  return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
714  }
715  if (VT.isInteger()) {
716  unsigned BitWidth = VT.getSizeInBits();
717  unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
718  return (BitWidth + RegWidth - 1) / RegWidth;
719  }
720  llvm_unreachable("Unsupported extended type!");
721  }
unsigned getSizeInBits() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
const TargetLoweringObjectFile& llvm::TargetLoweringBase::getObjFileLowering ( ) const
inlineinherited

Definition at line 151 of file TargetLowering.h.

151 { return TLOF; }
const TargetLoweringObjectFile & TLOF
True if this is a little endian target.
LegalizeAction llvm::TargetLoweringBase::getOperationAction ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 477 of file TargetLowering.h.

477  {
478  if (VT.isExtended()) return Expand;
479  // If a target-specific SDNode requires legalization, require the target
480  // to provide custom legalization for it.
481  if (Op > array_lengthof(OpActions[0])) return Custom;
482  unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
483  return (LegalizeAction)OpActions[I][Op];
484  }
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
#define I(x, y, z)
Definition: MD5.cpp:54
uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]
EVT AArch64TargetLowering::getOptimalMemOpType ( uint64_t  Size,
unsigned  DstAlign,
unsigned  SrcAlign,
bool  IsMemset,
bool  ZeroMemset,
bool  MemcpyStrSrc,
MachineFunction MF 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 6176 of file AArch64ISelLowering.cpp.

6180  {
6181  // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6182  // instruction to materialize the v2i64 zero and one store (with restrictive
6183  // addressing mode). Just do two i64 store of zero-registers.
6184  bool Fast;
6185  const Function *F = MF.getFunction();
6186  if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6189  (memOpAlign(SrcAlign, DstAlign, 16) ||
6190  (allowsUnalignedMemoryAccesses(MVT::f128, 0, &Fast) && Fast)))
6191  return MVT::f128;
6192 
6193  return Size >= 8 ? MVT::i64 : MVT::i32;
6194 }
F(f)
const Function * getFunction() const
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:872
const AArch64Subtarget * Subtarget
bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, bool *Fast=nullptr) const override
static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign, unsigned AlignCheck)
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:170
Disable implicit floating point insts.
Definition: Attributes.h:86
SDValue TargetLowering::getPICJumpTableRelocBase ( SDValue  Table,
SelectionDAG DAG 
) const
virtualinherited

Returns relocation base for the given PIC jumptable.

Reimplemented in llvm::X86TargetLowering.

Definition at line 235 of file TargetLowering.cpp.

236  {
237  // If our PIC model is GP relative, use the global offset table as the base.
238  unsigned JTEncoding = getJumpTableEncoding();
239 
240  if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
242  return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
243 
244  return Table;
245 }
virtual MVT getPointerTy(uint32_t=0) const
virtual unsigned getJumpTableEncoding() const
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Definition: SelectionDAG.h:631
const MCExpr * TargetLowering::getPICJumpTableRelocBaseExpr ( const MachineFunction MF,
unsigned  JTI,
MCContext Ctx 
) const
virtualinherited

This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.

getPICJumpTableRelocBaseExpr - This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.

Reimplemented in llvm::X86TargetLowering.

Definition at line 251 of file TargetLowering.cpp.

252  {
253  // The normal PIC reloc base is the label at the start of the jump table.
254  return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
255 }
static const MCSymbolRefExpr * Create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:293
MCSymbol * getJTISymbol(unsigned JTI, MCContext &Ctx, bool isLinkerPrivate=false) const
unsigned TargetLoweringBase::getPointerSizeInBits ( uint32_t  AS = 0) const
inherited

Definition at line 847 of file TargetLoweringBase.cpp.

847  {
848  return DL->getPointerSizeInBits(AS);
849 }
const DataLayout * DL
True if this is a little endian target.
unsigned getPointerSizeInBits(unsigned AS=0) const
Definition: DataLayout.h:313
MVT TargetLoweringBase::getPointerTy ( uint32_t  AS = 0) const
virtualinherited

Return the pointer type for the given address space, defaults to the pointer type from the data layout. FIXME: The default needs to be removed once all the code is updated.

Definition at line 843 of file TargetLoweringBase.cpp.

843  {
845 }
static MVT getIntegerVT(unsigned BitWidth)
unsigned getPointerSizeInBits(uint32_t AS=0) const
unsigned TargetLoweringBase::getPointerTypeSizeInBits ( Type Ty) const
inherited

Definition at line 851 of file TargetLoweringBase.cpp.

851  {
852  assert(Ty->isPointerTy());
854 }
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: Type.cpp:212
unsigned getPointerSizeInBits(uint32_t AS=0) const
assert(Globals.size() > 1)
bool isPointerTy() const
Definition: Type.h:217
bool AArch64TargetLowering::getPostIndexedAddressParts ( SDNode N,
SDNode Op,
SDValue Base,
SDValue Offset,
ISD::MemIndexedMode AM,
SelectionDAG DAG 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 7944 of file AArch64ISelLowering.cpp.

7946  {
7947  EVT VT;
7948  SDValue Ptr;
7949  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7950  VT = LD->getMemoryVT();
7951  Ptr = LD->getBasePtr();
7952  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7953  VT = ST->getMemoryVT();
7954  Ptr = ST->getBasePtr();
7955  } else
7956  return false;
7957 
7958  bool IsInc;
7959  if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
7960  return false;
7961  // Post-indexing updates the base, so it's not a valid transform
7962  // if that's not the same as the load's pointer.
7963  if (Ptr != Base)
7964  return false;
7965  AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
7966  return true;
7967 }
bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, bool &IsInc, SelectionDAG &DAG) const
TargetLoweringBase::LegalizeTypeAction AArch64TargetLowering::getPreferredVectorAction ( EVT  VT) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 8017 of file AArch64ISelLowering.cpp.

8017  {
8018  MVT SVT = VT.getSimpleVT();
8019  // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
8020  // v4i16, v2i32 instead of to promote.
8021  if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
8022  || SVT == MVT::v1f32)
8023  return TypeWidenVector;
8024 
8026 }
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
MVT getSimpleVT() const
Definition: ValueTypes.h:204
unsigned llvm::TargetLoweringBase::getPrefFunctionAlignment ( ) const
inlineinherited

Return the preferred function alignment.

Definition at line 878 of file TargetLowering.h.

878  {
879  return PrefFunctionAlignment;
880  }
unsigned llvm::TargetLoweringBase::getPrefLoopAlignment ( ) const
inlineinherited

Return the preferred loop alignment.

Definition at line 883 of file TargetLowering.h.

883  {
884  return PrefLoopAlignment;
885  }
unsigned PrefLoopAlignment
The preferred loop alignment.
bool AArch64TargetLowering::getPreIndexedAddressParts ( SDNode N,
SDValue Base,
SDValue Offset,
ISD::MemIndexedMode AM,
SelectionDAG DAG 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 7922 of file AArch64ISelLowering.cpp.

7925  {
7926  EVT VT;
7927  SDValue Ptr;
7928  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7929  VT = LD->getMemoryVT();
7930  Ptr = LD->getBasePtr();
7931  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7932  VT = ST->getMemoryVT();
7933  Ptr = ST->getBasePtr();
7934  } else
7935  return false;
7936 
7937  bool IsInc;
7938  if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
7939  return false;
7940  AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
7941  return true;
7942 }
bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, bool &IsInc, SelectionDAG &DAG) const
SDNode * getNode() const
get the SDNode which holds the desired result
virtual const TargetRegisterClass* llvm::TargetLoweringBase::getRegClassFor ( MVT  VT) const
inlinevirtualinherited

Return the register class that should be used for the specified value type.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 314 of file TargetLowering.h.

314  {
315  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
316  assert(RC && "This value type is not natively supported!");
317  return RC;
318  }
assert(Globals.size() > 1)
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
std::pair< unsigned, const TargetRegisterClass * > AArch64TargetLowering::getRegForInlineAsmConstraint ( const std::string &  Constraint,
MVT  VT 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 3907 of file AArch64ISelLowering.cpp.

3908  {
3909  if (Constraint.size() == 1) {
3910  switch (Constraint[0]) {
3911  case 'r':
3912  if (VT.getSizeInBits() == 64)
3913  return std::make_pair(0U, &AArch64::GPR64commonRegClass);
3914  return std::make_pair(0U, &AArch64::GPR32commonRegClass);
3915  case 'w':
3916  if (VT == MVT::f32)
3917  return std::make_pair(0U, &AArch64::FPR32RegClass);
3918  if (VT.getSizeInBits() == 64)
3919  return std::make_pair(0U, &AArch64::FPR64RegClass);
3920  if (VT.getSizeInBits() == 128)
3921  return std::make_pair(0U, &AArch64::FPR128RegClass);
3922  break;
3923  // The instructions that this constraint is designed for can
3924  // only take 128-bit registers so just use that regclass.
3925  case 'x':
3926  if (VT.getSizeInBits() == 128)
3927  return std::make_pair(0U, &AArch64::FPR128_loRegClass);
3928  break;
3929  }
3930  }
3931  if (StringRef("{cc}").equals_lower(Constraint))
3932  return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
3933 
3934  // Use the default implementation in TargetLowering to convert the register
3935  // constraint into a member of a register class.
3936  std::pair<unsigned, const TargetRegisterClass *> Res;
3937  Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3938 
3939  // Not found as a standard register?
3940  if (!Res.second) {
3941  unsigned Size = Constraint.size();
3942  if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
3943  tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
3944  const std::string Reg =
3945  std::string(&Constraint[2], &Constraint[Size - 1]);
3946  int RegNo = atoi(Reg.c_str());
3947  if (RegNo >= 0 && RegNo <= 31) {
3948  // v0 - v31 are aliases of q0 - q31.
3949  // By default we'll emit v0-v31 for this unless there's a modifier where
3950  // we'll emit the correct register as well.
3951  Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
3952  Res.second = &AArch64::FPR128RegClass;
3953  }
3954  }
3955  }
3956 
3957  return Res;
3958 }
unsigned getSizeInBits() const
::std::string string
Definition: gtest-port.h:766
Reg
All possible values of the reg field in the ModR/M byte.
int atoi(const char *str);
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
Definition: StringRef.h:141
unsigned AArch64TargetLowering::getRegisterByName ( const char *  RegName,
EVT  VT 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 3684 of file AArch64ISelLowering.cpp.

3685  {
3686  unsigned Reg = StringSwitch<unsigned>(RegName)
3687  .Case("sp", AArch64::SP)
3688  .Default(0);
3689  if (Reg)
3690  return Reg;
3691  report_fatal_error("Invalid register name global variable");
3692 }
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reg
All possible values of the reg field in the ModR/M byte.
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
R Default(const T &Value) const
Definition: StringSwitch.h:111
MVT llvm::TargetLoweringBase::getRegisterType ( MVT  VT) const
inlineinherited

Return the type of registers that this ValueType will eventually require.

Definition at line 669 of file TargetLowering.h.

669  {
670  assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
671  return RegisterTypeForVT[VT.SimpleTy];
672  }
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
MVT llvm::TargetLoweringBase::getRegisterType ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

Return the type of registers that this ValueType will eventually require.

Definition at line 675 of file TargetLowering.h.

675  {
676  if (VT.isSimple()) {
677  assert((unsigned)VT.getSimpleVT().SimpleTy <
679  return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
680  }
681  if (VT.isVector()) {
682  EVT VT1;
683  MVT RegisterVT;
684  unsigned NumIntermediates;
685  (void)getVectorTypeBreakdown(Context, VT, VT1,
686  NumIntermediates, RegisterVT);
687  return RegisterVT;
688  }
689  if (VT.isInteger()) {
690  return getRegisterType(Context, getTypeToTransformTo(Context, VT));
691  }
692  llvm_unreachable("Unsupported extended type!");
693  }
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
virtual uint8_t llvm::TargetLoweringBase::getRepRegClassCostFor ( MVT  VT) const
inlinevirtualinherited

Return the cost of the 'representative' register class for the specified value type.

Definition at line 334 of file TargetLowering.h.

334  {
335  return RepRegClassCostForVT[VT.SimpleTy];
336  }
uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]
virtual const TargetRegisterClass* llvm::TargetLoweringBase::getRepRegClassFor ( MVT  VT) const
inlinevirtualinherited

Return the 'representative' register class for the specified value type.

The 'representative' register class is the largest legal super-reg register class for the register class of the value type. For example, on i386 the rep register class for i8, i16, and i32 are GR32; while the rep register class is GR64 on x86_64.

Reimplemented in llvm::MipsSETargetLowering.

Definition at line 327 of file TargetLowering.h.

327  {
328  const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
329  return RC;
330  }
const TargetRegisterClass * RepRegClassForVT[MVT::LAST_VALUETYPE]
MVT AArch64TargetLowering::getScalarShiftAmountTy ( EVT  LHSTy) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 629 of file AArch64ISelLowering.cpp.

629  {
630  return MVT::i64;
631 }
int AArch64TargetLowering::getScalingFactorCost ( const AddrMode AM,
Type Ty 
) const
overridevirtual

Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 6264 of file AArch64ISelLowering.cpp.

6265  {
6266  // Scaling factors are not free at all.
6267  // Operands | Rt Latency
6268  // -------------------------------------------
6269  // Rt, [Xn, Xm] | 4
6270  // -------------------------------------------
6271  // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6272  // Rt, [Xn, Wm, <extend> #imm] |
6273  if (isLegalAddressingMode(AM, Ty))
6274  // Scale represents reg2 * scale, thus account for 1 if
6275  // it is not equal to 0 or 1.
6276  return AM.Scale != 0 && AM.Scale != 1;
6277  return -1;
6278 }
bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override
Sched::Preference llvm::TargetLoweringBase::getSchedulingPreference ( ) const
inlineinherited

Return target scheduling preference.

Definition at line 301 of file TargetLowering.h.

301  {
302  return SchedPreferenceInfo;
303  }
Sched::Preference SchedPreferenceInfo
virtual Sched::Preference llvm::TargetLoweringBase::getSchedulingPreference ( SDNode ) const
inlinevirtualinherited

Some scheduler, e.g. hybrid, can switch to different scheduling heuristics for different nodes. This function returns the preference (or none) for the given node.

Reimplemented in llvm::PPCTargetLowering, and llvm::ARMTargetLowering.

Definition at line 308 of file TargetLowering.h.

308  {
309  return Sched::None;
310  }
const MCPhysReg * AArch64TargetLowering::getScratchRegisters ( CallingConv::ID  CC) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 6298 of file AArch64ISelLowering.cpp.

6298  {
6299  // LR is a callee-save register, but we must treat it as clobbered by any call
6300  // site. Hence we include LR in the scratch registers, which are in turn added
6301  // as implicit-defs for stackmaps and patchpoints.
6302  static const MCPhysReg ScratchRegs[] = {
6303  AArch64::X16, AArch64::X17, AArch64::LR, 0
6304  };
6305  return ScratchRegs;
6306 }
uint16_t MCPhysReg
EVT AArch64TargetLowering::getSetCCResultType ( LLVMContext Context,
EVT  VT 
) const
overridevirtual

getSetCCResultType - Return the ISD::SETCC ValueType

Reimplemented from llvm::TargetLoweringBase.

Definition at line 560 of file AArch64ISelLowering.cpp.

560  {
561  if (!VT.isVector())
562  return MVT::i32;
564 }
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
EVT changeVectorElementTypeToInteger() const
Definition: ValueTypes.h:81
EVT TargetLoweringBase::getShiftAmountTy ( EVT  LHSTy) const
inherited

Definition at line 860 of file TargetLoweringBase.cpp.

860  {
861  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
862  if (LHSTy.isVector())
863  return LHSTy;
864  return getScalarShiftAmountTy(LHSTy);
865 }
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
assert(Globals.size() > 1)
MVT llvm::TargetLoweringBase::getSimpleValueType ( Type Ty,
bool  AllowUnknown = false 
) const
inlineinherited

Return the MVT corresponding to this LLVM type. See getValueType.

Definition at line 659 of file TargetLowering.h.

659  {
660  return getValueType(Ty, AllowUnknown).getSimpleVT();
661  }
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
MVT getSimpleVT() const
Definition: ValueTypes.h:204
TargetLowering::ConstraintWeight AArch64TargetLowering::getSingleConstraintMatchWeight ( AsmOperandInfo info,
const char *  constraint 
) const
overrideprivatevirtual

Examine constraint string and operand type and determine a weight value. The operand object must already have been set up with the operand type.

Examine constraint type and operand type and determine a weight value. This object must already have been set up with the operand type and the current alternative constraint selected.

Reimplemented from llvm::TargetLowering.

Definition at line 3880 of file AArch64ISelLowering.cpp.

3881  {
3882  ConstraintWeight weight = CW_Invalid;
3883  Value *CallOperandVal = info.CallOperandVal;
3884  // If we don't have a value, we can't do a match,
3885  // but allow it at the lowest weight.
3886  if (!CallOperandVal)
3887  return CW_Default;
3888  Type *type = CallOperandVal->getType();
3889  // Look at the constraint type.
3890  switch (*constraint) {
3891  default:
3893  break;
3894  case 'x':
3895  case 'w':
3896  if (type->isFloatingPointTy() || type->isVectorTy())
3897  weight = CW_Register;
3898  break;
3899  case 'z':
3900  weight = CW_Constant;
3901  break;
3902  }
3903  return weight;
3904 }
lazy value info
bool isFloatingPointTy() const
Definition: Type.h:159
bool isVectorTy() const
Definition: Type.h:226
Type * getType() const
Definition: Value.h:215
LLVM Value Representation.
Definition: Value.h:69
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
virtual bool llvm::TargetLoweringBase::getStackCookieLocation ( unsigned &  ,
unsigned &   
) const
inlinevirtualinherited

Return true if the target stores stack protector cookies at a fixed offset in some non-standard address space, and populates the address space and offset as appropriate.

Reimplemented in llvm::X86TargetLowering.

Definition at line 896 of file TargetLowering.h.

897  {
898  return false;
899  }
unsigned llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore ( ) const
inlineinherited

If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

Definition at line 839 of file TargetLowering.h.

839  {
841  }
unsigned StackPointerRegisterToSaveRestore
const TargetMachine& llvm::TargetLoweringBase::getTargetMachine ( ) const
inlineinherited

Definition at line 149 of file TargetLowering.h.

149 { return TM; }
const TargetMachine & TM
True if this is a little endian target.
const char * AArch64TargetLowering::getTargetNodeName ( unsigned  Opcode) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 646 of file AArch64ISelLowering.cpp.

646  {
647  switch (Opcode) {
648  default:
649  return nullptr;
650  case AArch64ISD::CALL: return "AArch64ISD::CALL";
651  case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
652  case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
653  case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
654  case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
655  case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
656  case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
657  case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
658  case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
659  case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
660  case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
661  case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
662  case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL";
663  case AArch64ISD::ADC: return "AArch64ISD::ADC";
664  case AArch64ISD::SBC: return "AArch64ISD::SBC";
665  case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
666  case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
667  case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
668  case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
669  case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
670  case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
671  case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
672  case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
673  case AArch64ISD::DUP: return "AArch64ISD::DUP";
674  case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
675  case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
676  case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
677  case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
678  case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
679  case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
680  case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
681  case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
682  case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
683  case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
684  case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
685  case AArch64ISD::BICi: return "AArch64ISD::BICi";
686  case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
687  case AArch64ISD::BSL: return "AArch64ISD::BSL";
688  case AArch64ISD::NEG: return "AArch64ISD::NEG";
689  case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
690  case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
691  case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
692  case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
693  case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
694  case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
695  case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
696  case AArch64ISD::REV16: return "AArch64ISD::REV16";
697  case AArch64ISD::REV32: return "AArch64ISD::REV32";
698  case AArch64ISD::REV64: return "AArch64ISD::REV64";
699  case AArch64ISD::EXT: return "AArch64ISD::EXT";
700  case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
701  case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
702  case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
703  case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
704  case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
705  case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
706  case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
707  case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
708  case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
709  case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
710  case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
711  case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
712  case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
713  case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
714  case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
715  case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
716  case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
717  case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
718  case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
719  case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
720  case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
721  case AArch64ISD::NOT: return "AArch64ISD::NOT";
722  case AArch64ISD::BIT: return "AArch64ISD::BIT";
723  case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
724  case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
725  case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
726  case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
727  case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
728  case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
729  case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
730  case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
731  case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
732  case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
733  case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
734  case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
735  case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
736  case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
737  case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
738  case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
739  case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
740  case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
741  case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
742  case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
743  case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
744  case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
745  case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
746  case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
747  case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
748  case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
749  case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
750  case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
751  case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
752  case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
753  case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
754  case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
755  case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
756  case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
757  case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
758  case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
759  }
760 }
bool AArch64TargetLowering::getTgtMemIntrinsic ( IntrinsicInfo Info,
const CallInst I,
unsigned  Intrinsic 
) const
overridevirtual

getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes. The associated MachineMemOperands record the alignment specified in the intrinsic calls.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 5989 of file AArch64ISelLowering.cpp.

5991  {
5992  switch (Intrinsic) {
5993  case Intrinsic::aarch64_neon_ld2:
5994  case Intrinsic::aarch64_neon_ld3:
5995  case Intrinsic::aarch64_neon_ld4:
5996  case Intrinsic::aarch64_neon_ld1x2:
5997  case Intrinsic::aarch64_neon_ld1x3:
5998  case Intrinsic::aarch64_neon_ld1x4:
5999  case Intrinsic::aarch64_neon_ld2lane:
6000  case Intrinsic::aarch64_neon_ld3lane:
6001  case Intrinsic::aarch64_neon_ld4lane:
6002  case Intrinsic::aarch64_neon_ld2r:
6003  case Intrinsic::aarch64_neon_ld3r:
6004  case Intrinsic::aarch64_neon_ld4r: {
6005  Info.opc = ISD::INTRINSIC_W_CHAIN;
6006  // Conservatively set memVT to the entire set of vectors loaded.
6007  uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
6008  Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6009  Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6010  Info.offset = 0;
6011  Info.align = 0;
6012  Info.vol = false; // volatile loads with NEON intrinsics not supported
6013  Info.readMem = true;
6014  Info.writeMem = false;
6015  return true;
6016  }
6017  case Intrinsic::aarch64_neon_st2:
6018  case Intrinsic::aarch64_neon_st3:
6019  case Intrinsic::aarch64_neon_st4:
6020  case Intrinsic::aarch64_neon_st1x2:
6021  case Intrinsic::aarch64_neon_st1x3:
6022  case Intrinsic::aarch64_neon_st1x4:
6023  case Intrinsic::aarch64_neon_st2lane:
6024  case Intrinsic::aarch64_neon_st3lane:
6025  case Intrinsic::aarch64_neon_st4lane: {
6026  Info.opc = ISD::INTRINSIC_VOID;
6027  // Conservatively set memVT to the entire set of vectors stored.
6028  unsigned NumElts = 0;
6029  for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6030  Type *ArgTy = I.getArgOperand(ArgI)->getType();
6031  if (!ArgTy->isVectorTy())
6032  break;
6033  NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6034  }
6035  Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6036  Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6037  Info.offset = 0;
6038  Info.align = 0;
6039  Info.vol = false; // volatile stores with NEON intrinsics not supported
6040  Info.readMem = false;
6041  Info.writeMem = true;
6042  return true;
6043  }
6044  case Intrinsic::aarch64_ldaxr:
6045  case Intrinsic::aarch64_ldxr: {
6046  PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6047  Info.opc = ISD::INTRINSIC_W_CHAIN;
6048  Info.memVT = MVT::getVT(PtrTy->getElementType());
6049  Info.ptrVal = I.getArgOperand(0);
6050  Info.offset = 0;
6051  Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6052  Info.vol = true;
6053  Info.readMem = true;
6054  Info.writeMem = false;
6055  return true;
6056  }
6057  case Intrinsic::aarch64_stlxr:
6058  case Intrinsic::aarch64_stxr: {
6059  PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6060  Info.opc = ISD::INTRINSIC_W_CHAIN;
6061  Info.memVT = MVT::getVT(PtrTy->getElementType());
6062  Info.ptrVal = I.getArgOperand(1);
6063  Info.offset = 0;
6064  Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6065  Info.vol = true;
6066  Info.readMem = false;
6067  Info.writeMem = true;
6068  return true;
6069  }
6070  case Intrinsic::aarch64_ldaxp:
6071  case Intrinsic::aarch64_ldxp: {
6072  Info.opc = ISD::INTRINSIC_W_CHAIN;
6073  Info.memVT = MVT::i128;
6074  Info.ptrVal = I.getArgOperand(0);
6075  Info.offset = 0;
6076  Info.align = 16;
6077  Info.vol = true;
6078  Info.readMem = true;
6079  Info.writeMem = false;
6080  return true;
6081  }
6082  case Intrinsic::aarch64_stlxp:
6083  case Intrinsic::aarch64_stxp: {
6084  Info.opc = ISD::INTRINSIC_W_CHAIN;
6085  Info.memVT = MVT::i128;
6086  Info.ptrVal = I.getArgOperand(2);
6087  Info.offset = 0;
6088  Info.align = 16;
6089  Info.vol = true;
6090  Info.readMem = false;
6091  Info.writeMem = true;
6092  return true;
6093  }
6094  default:
6095  break;
6096  }
6097 
6098  return false;
6099 }
unsigned getNumArgOperands() const
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
Definition: Type.h:125
Type * getElementType() const
Definition: DerivedTypes.h:319
bool isVectorTy() const
Definition: Type.h:226
const DataLayout * getDataLayout() const
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Definition: ValueTypes.cpp:247
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
unsigned getABITypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:683
uint64_t getTypeAllocSize(Type *Ty) const
Definition: DataLayout.h:368
Type * getType() const
Definition: Value.h:215
Value * getArgOperand(unsigned i) const
LegalizeAction llvm::TargetLoweringBase::getTruncStoreAction ( MVT  ValVT,
MVT  MemVT 
) const
inlineinherited

Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 535 of file TargetLowering.h.

535  {
536  assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
537  "Table isn't big enough!");
538  return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy]
539  [MemVT.SimpleTy];
540  }
uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
assert(Globals.size() > 1)
LegalizeTypeAction llvm::TargetLoweringBase::getTypeAction ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). 'Custom' is not an option.

Definition at line 375 of file TargetLowering.h.

375  {
376  return getTypeConversion(Context, VT).first;
377  }
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Reset the operation actions based on target options.
LegalizeTypeAction llvm::TargetLoweringBase::getTypeAction ( MVT  VT) const
inlineinherited

Definition at line 378 of file TargetLowering.h.

378  {
379  return ValueTypeActions.getTypeAction(VT);
380  }
LegalizeTypeAction getTypeAction(MVT VT) const
ValueTypeActionImpl ValueTypeActions
True if this is a little endian target.
LegalizeKind llvm::TargetLoweringBase::getTypeConversion ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

Reset the operation actions based on target options.

Definition at line 1629 of file TargetLowering.h.

1629  {
1630  // If this is a simple type, use the ComputeRegisterProp mechanism.
1631  if (VT.isSimple()) {
1632  MVT SVT = VT.getSimpleVT();
1633  assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1634  MVT NVT = TransformToType[SVT.SimpleTy];
1636 
1637  assert(
1638  (LA == TypeLegal || LA == TypeSoftenFloat ||
1640  && "Promote may not follow Expand or Promote");
1641 
1642  if (LA == TypeSplitVector)
1643  return LegalizeKind(LA, EVT::getVectorVT(Context,
1644  SVT.getVectorElementType(),
1645  SVT.getVectorNumElements()/2));
1646  if (LA == TypeScalarizeVector)
1647  return LegalizeKind(LA, SVT.getVectorElementType());
1648  return LegalizeKind(LA, NVT);
1649  }
1650 
1651  // Handle Extended Scalar Types.
1652  if (!VT.isVector()) {
1653  assert(VT.isInteger() && "Float types must be simple");
1654  unsigned BitSize = VT.getSizeInBits();
1655  // First promote to a power-of-two size, then expand if necessary.
1656  if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1657  EVT NVT = VT.getRoundIntegerType(Context);
1658  assert(NVT != VT && "Unable to round integer VT");
1659  LegalizeKind NextStep = getTypeConversion(Context, NVT);
1660  // Avoid multi-step promotion.
1661  if (NextStep.first == TypePromoteInteger) return NextStep;
1662  // Return rounded integer type.
1663  return LegalizeKind(TypePromoteInteger, NVT);
1664  }
1665 
1667  EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1668  }
1669 
1670  // Handle vector types.
1671  unsigned NumElts = VT.getVectorNumElements();
1672  EVT EltVT = VT.getVectorElementType();
1673 
1674  // Vectors with only one element are always scalarized.
1675  if (NumElts == 1)
1676  return LegalizeKind(TypeScalarizeVector, EltVT);
1677 
1678  // Try to widen vector elements until the element type is a power of two and
1679  // promote it to a legal type later on, for example:
1680  // <3 x i8> -> <4 x i8> -> <4 x i32>
1681  if (EltVT.isInteger()) {
1682  // Vectors with a number of elements that is not a power of two are always
1683  // widened, for example <3 x i8> -> <4 x i8>.
1684  if (!VT.isPow2VectorType()) {
1685  NumElts = (unsigned)NextPowerOf2(NumElts);
1686  EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1687  return LegalizeKind(TypeWidenVector, NVT);
1688  }
1689 
1690  // Examine the element type.
1691  LegalizeKind LK = getTypeConversion(Context, EltVT);
1692 
1693  // If type is to be expanded, split the vector.
1694  // <4 x i140> -> <2 x i140>
1695  if (LK.first == TypeExpandInteger)
1697  EVT::getVectorVT(Context, EltVT, NumElts / 2));
1698 
1699  // Promote the integer element types until a legal vector type is found
1700  // or until the element integer type is too big. If a legal type was not
1701  // found, fallback to the usual mechanism of widening/splitting the
1702  // vector.
1703  EVT OldEltVT = EltVT;
1704  while (1) {
1705  // Increase the bitwidth of the element to the next pow-of-two
1706  // (which is greater than 8 bits).
1707  EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1708  ).getRoundIntegerType(Context);
1709 
1710  // Stop trying when getting a non-simple element type.
1711  // Note that vector elements may be greater than legal vector element
1712  // types. Example: X86 XMM registers hold 64bit element on 32bit
1713  // systems.
1714  if (!EltVT.isSimple()) break;
1715 
1716  // Build a new vector type and check if it is legal.
1717  MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1718  // Found a legal promoted vector type.
1719  if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1721  EVT::getVectorVT(Context, EltVT, NumElts));
1722  }
1723 
1724  // Reset the type to the unexpanded type if we did not find a legal vector
1725  // type with a promoted vector element type.
1726  EltVT = OldEltVT;
1727  }
1728 
1729  // Try to widen the vector until a legal type is found.
1730  // If there is no wider legal type, split the vector.
1731  while (1) {
1732  // Round up to the next power of 2.
1733  NumElts = (unsigned)NextPowerOf2(NumElts);
1734 
1735  // If there is no simple vector type with this many elements then there
1736  // cannot be a larger legal vector type. Note that this assumes that
1737  // there are no skipped intermediate vector types in the simple types.
1738  if (!EltVT.isSimple()) break;
1739  MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1740  if (LargerVector == MVT()) break;
1741 
1742  // If this type is legal then widen the vector.
1743  if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1744  return LegalizeKind(TypeWidenVector, LargerVector);
1745  }
1746 
1747  // Widen odd vectors to next power of two.
1748  if (!VT.isPow2VectorType()) {
1749  EVT NVT = VT.getPow2VectorType(Context);
1750  return LegalizeKind(TypeWidenVector, NVT);
1751  }
1752 
1753  // Vectors with illegal element types are expanded.
1754  EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1755  return LegalizeKind(TypeSplitVector, NVT);
1756  }
static MVT getVectorVT(MVT VT, unsigned NumElements)
MVT TransformToType[MVT::LAST_VALUETYPE]
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
LegalizeTypeAction getTypeAction(MVT VT) const
uint64_t NextPowerOf2(uint64_t A)
Definition: MathExtras.h:567
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
ValueTypeActionImpl ValueTypeActions
True if this is a little endian target.
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Reset the operation actions based on target options.
bool isPowerOf2_32(uint32_t Value)
Definition: MathExtras.h:363
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Definition: ValueTypes.h:62
virtual MVT llvm::TargetLowering::getTypeForExtArgOrReturn ( MVT  VT,
ISD::NodeType   
) const
inlinevirtualinherited

Return the type that should be used to zero or sign extend a zeroext/signext integer argument or return value. FIXME: Most C calling convention requires the return type to be promoted, but this is not true all the time, e.g. i1 on x86-64. It is also not necessary for non-C calling conventions. The frontend should handle this and include all of the necessary information.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2327 of file TargetLowering.h.

2328  {
2329  MVT MinVT = getRegisterType(MVT::i32);
2330  return VT.bitsLT(MinVT) ? MinVT : VT;
2331  }
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
std::pair< unsigned, MVT > TargetLoweringBase::getTypeLegalizationCost ( Type Ty) const
inherited

Estimate the cost of type-legalization and the legalized type.

Definition at line 1425 of file TargetLoweringBase.cpp.

1425  {
1426  LLVMContext &C = Ty->getContext();
1427  EVT MTy = getValueType(Ty);
1428 
1429  unsigned Cost = 1;
1430  // We keep legalizing the type until we find a legal kind. We assume that
1431  // the only operation that costs anything is the split. After splitting
1432  // we need to handle two types.
1433  while (true) {
1434  LegalizeKind LK = getTypeConversion(C, MTy);
1435 
1436  if (LK.first == TypeLegal)
1437  return std::make_pair(Cost, MTy.getSimpleVT());
1438 
1439  if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1440  Cost *= 2;
1441 
1442  // Keep legalizing the type.
1443  MTy = LK.second;
1444  }
1445 }
std::pair< LegalizeTypeAction, EVT > LegalizeKind
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
Definition: Type.h:125
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Reset the operation actions based on target options.
MVT getSimpleVT() const
Definition: ValueTypes.h:204
EVT llvm::TargetLoweringBase::getTypeToExpandTo ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

For types supported by the target, this is an identity function. For types that must be expanded (i.e. integer types that are larger than the largest integer register or illegal floating point types), this returns the largest legal type it will be expanded to.

Definition at line 396 of file TargetLowering.h.

396  {
397  assert(!VT.isVector());
398  while (true) {
399  switch (getTypeAction(Context, VT)) {
400  case TypeLegal:
401  return VT;
402  case TypeExpandInteger:
403  VT = getTypeToTransformTo(Context, VT);
404  break;
405  default:
406  llvm_unreachable("Type is not legal nor is it to be expanded!");
407  }
408  }
409  }
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
assert(Globals.size() > 1)
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
MVT llvm::TargetLoweringBase::getTypeToPromoteTo ( unsigned  Op,
MVT  VT 
) const
inlineinherited

If the action for this operation is to promote, this method returns the ValueType to promote to.

Definition at line 611 of file TargetLowering.h.

611  {
612  assert(getOperationAction(Op, VT) == Promote &&
613  "This operation isn't promoted!");
614 
615  // See if this has an explicit type specified.
616  std::map<std::pair<unsigned, MVT::SimpleValueType>,
617  MVT::SimpleValueType>::const_iterator PTTI =
618  PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
619  if (PTTI != PromoteToType.end()) return PTTI->second;
620 
621  assert((VT.isInteger() || VT.isFloatingPoint()) &&
622  "Cannot autopromote this type, add it with AddPromotedToType.");
623 
624  MVT NVT = VT;
625  do {
626  NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
627  assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
628  "Didn't find type to promote to!");
629  } while (!isTypeLegal(NVT) ||
630  getOperationAction(Op, NVT) == Promote);
631  return NVT;
632  }
std::map< std::pair< unsigned, MVT::SimpleValueType >, MVT::SimpleValueType > PromoteToType
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
EVT llvm::TargetLoweringBase::getTypeToTransformTo ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

For types supported by the target, this is an identity function. For types that must be promoted to larger types, this returns the larger type to promote to. For integer types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register. For illegal floating point types, this returns the integer type to transform to.

Definition at line 388 of file TargetLowering.h.

388  {
389  return getTypeConversion(Context, VT).second;
390  }
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Reset the operation actions based on target options.
EVT llvm::TargetLoweringBase::getValueType ( Type Ty,
bool  AllowUnknown = false 
) const
inlineinherited

Return the EVT corresponding to this LLVM type. This is fixed by the LLVM operations except for the pointer size. If AllowUnknown is true, this will return MVT::Other for types with no EVT counterpart (e.g. structs), otherwise it will assert.

Definition at line 638 of file TargetLowering.h.

638  {
639  // Lower scalar pointers to native pointer types.
640  if (PointerType *PTy = dyn_cast<PointerType>(Ty))
641  return getPointerTy(PTy->getAddressSpace());
642 
643  if (Ty->isVectorTy()) {
644  VectorType *VTy = cast<VectorType>(Ty);
645  Type *Elm = VTy->getElementType();
646  // Lower vectors of pointers to native pointer types.
647  if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
648  EVT PointerTy(getPointerTy(PT->getAddressSpace()));
649  Elm = PointerTy.getTypeForEVT(Ty->getContext());
650  }
651 
652  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
653  VTy->getNumElements());
654  }
655  return EVT::getEVT(Ty, AllowUnknown);
656  }
void * PointerTy
Definition: GenericValue.h:23
virtual MVT getPointerTy(uint32_t=0) const
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Definition: ValueTypes.cpp:275
RelocType Type
Definition: COFFYAML.cpp:285
const ValueTypeActionImpl& llvm::TargetLoweringBase::getValueTypeActions ( ) const
inlineinherited

Definition at line 367 of file TargetLowering.h.

367  {
368  return ValueTypeActions;
369  }
ValueTypeActionImpl ValueTypeActions
True if this is a little endian target.
virtual MVT llvm::TargetLoweringBase::getVectorIdxTy ( ) const
inlinevirtualinherited

Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 169 of file TargetLowering.h.

169  {
170  return getPointerTy();
171  }
virtual MVT getPointerTy(uint32_t=0) const
unsigned TargetLoweringBase::getVectorTypeBreakdown ( LLVMContext Context,
EVT  VT,
EVT IntermediateVT,
unsigned &  NumIntermediates,
MVT RegisterVT 
) const
inherited

Vector types are broken down into some number of legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.

This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.

getVectorTypeBreakdown - Vector types are broken down into some number of legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.

This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.

Definition at line 1227 of file TargetLoweringBase.cpp.

1230  {
1231  unsigned NumElts = VT.getVectorNumElements();
1232 
1233  // If there is a wider vector type with the same element type as this one,
1234  // or a promoted vector type that has the same number of elements which
1235  // are wider, then we should convert to that legal vector type.
1236  // This handles things like <2 x float> -> <4 x float> and
1237  // <4 x i1> -> <4 x i32>.
1238  LegalizeTypeAction TA = getTypeAction(Context, VT);
1239  if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1240  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1241  if (isTypeLegal(RegisterEVT)) {
1242  IntermediateVT = RegisterEVT;
1243  RegisterVT = RegisterEVT.getSimpleVT();
1244  NumIntermediates = 1;
1245  return 1;
1246  }
1247  }
1248 
1249  // Figure out the right, legal destination reg to copy into.
1250  EVT EltTy = VT.getVectorElementType();
1251 
1252  unsigned NumVectorRegs = 1;
1253 
1254  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1255  // could break down into LHS/RHS like LegalizeDAG does.
1256  if (!isPowerOf2_32(NumElts)) {
1257  NumVectorRegs = NumElts;
1258  NumElts = 1;
1259  }
1260 
1261  // Divide the input until we get to a supported size. This will always
1262  // end with a scalar if the target doesn't support vectors.
1263  while (NumElts > 1 && !isTypeLegal(
1264  EVT::getVectorVT(Context, EltTy, NumElts))) {
1265  NumElts >>= 1;
1266  NumVectorRegs <<= 1;
1267  }
1268 
1269  NumIntermediates = NumVectorRegs;
1270 
1271  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1272  if (!isTypeLegal(NewVT))
1273  NewVT = EltTy;
1274  IntermediateVT = NewVT;
1275 
1276  MVT DestVT = getRegisterType(Context, NewVT);
1277  RegisterVT = DestVT;
1278  unsigned NewVTSize = NewVT.getSizeInBits();
1279 
1280  // Convert sizes such as i33 to i64.
1281  if (!isPowerOf2_32(NewVTSize))
1282  NewVTSize = NextPowerOf2(NewVTSize);
1283 
1284  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1285  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1286 
1287  // Otherwise, promotion or legal types use the same number of registers as
1288  // the vector decimated to the appropriate level.
1289  return NumVectorRegs;
1290 }
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
unsigned getSizeInBits() const
EVT getVectorElementType() const
Definition: ValueTypes.h:217
bool isTypeLegal(EVT VT) const
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
uint64_t NextPowerOf2(uint64_t A)
Definition: MathExtras.h:567
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
bool isPowerOf2_32(uint32_t Value)
Definition: MathExtras.h:363
MVT getSimpleVT() const
Definition: ValueTypes.h:204
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
virtual void llvm::TargetLowering::HandleByVal ( CCState ,
unsigned &  ,
unsigned   
) const
inlinevirtualinherited

Target-specific cleanup for formal ByVal parameters.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 2266 of file TargetLowering.h.

2266 {}
bool llvm::TargetLoweringBase::hasBigEndianPartOrdering ( EVT  VT) const
inlineinherited

When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first.

Definition at line 731 of file TargetLowering.h.

731  {
732  return isBigEndian() || VT == MVT::ppcf128;
733  }
bool llvm::TargetLoweringBase::hasExtractBitsInsn ( ) const
inlineinherited

Return true if the target has BitExtract instructions.

Definition at line 186 of file TargetLowering.h.

bool llvm::TargetLoweringBase::hasMultipleConditionRegisters ( ) const
inlineinherited

Return true if multiple condition registers are available.

Definition at line 181 of file TargetLowering.h.

181  {
183  }
bool AArch64TargetLowering::hasPairedLoad ( Type LoadedType,
unsigned &  RequiredAligment 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 6149 of file AArch64ISelLowering.cpp.

6150  {
6151  if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6152  return false;
6153  // Cyclone supports unaligned accesses.
6154  RequiredAligment = 0;
6155  unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6156  return NumBits == 32 || NumBits == 64;
6157 }
bool isFloatTy() const
isFloatTy - Return true if this is 'float', a 32-bit IEEE fp type.
Definition: Type.h:143
bool isIntegerTy() const
Definition: Type.h:193
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
bool AArch64TargetLowering::hasPairedLoad ( EVT  LoadedType,
unsigned &  RequiredAligment 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 6159 of file AArch64ISelLowering.cpp.

6160  {
6161  if (!LoadedType.isSimple() ||
6162  (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6163  return false;
6164  // Cyclone supports unaligned accesses.
6165  RequiredAligment = 0;
6166  unsigned NumBits = LoadedType.getSizeInBits();
6167  return NumBits == 32 || NumBits == 64;
6168 }
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
bool isSimple() const
Definition: ValueTypes.h:95
bool llvm::TargetLoweringBase::hasTargetDAGCombine ( ISD::NodeType  NT) const
inlineinherited

If true, the target has custom DAG combine transformations that it can perform for the specified node.

Definition at line 737 of file TargetLowering.h.

737  {
738  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
739  return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
740  }
unsigned char TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
void TargetLoweringBase::initActions ( )
protectedinherited

Initialize all of the actions to default values.

Definition at line 733 of file TargetLoweringBase.cpp.

733  {
734  // All operations default to being supported.
735  memset(OpActions, 0, sizeof(OpActions));
736  memset(LoadExtActions, 0, sizeof(LoadExtActions));
742 
743  // Set default actions for various operations.
744  for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
745  // Default all indexed load / store to expand.
746  for (unsigned IM = (unsigned)ISD::PRE_INC;
747  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
750  }
751 
752  // Most backends expect to see the node which just returns the value loaded.
755 
756  // These operations default to expand.
759 
760  // These library functions default to expand.
762 
763  // These operations default to expand for vector types.
764  if (VT >= MVT::FIRST_VECTOR_VALUETYPE &&
773  }
774  }
775 
776  // Most targets ignore the @llvm.prefetch intrinsic.
778 
779  // ConstantFP nodes default to expand. Targets can either change this to
780  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
781  // to optimize expansions for certain constants.
787 
788  // These library functions default to expand.
833 
834  // Default ISD::TRAP to expand (which turns it into abort).
836 
837  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
838  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
839  //
841 }
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
unsigned char TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:622
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:625
void *memset(void *b, int c, size_t len);
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE+15)/16]
uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
int TargetLoweringBase::InstructionOpcodeToISD ( unsigned  Opcode) const
inherited

Get the ISD node that corresponds to the Instruction class opcode.

Definition at line 1353 of file TargetLoweringBase.cpp.

1353  {
1354  enum InstructionOpcodes {
1355 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1356 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1357 #include "llvm/IR/Instruction.def"
1358  };
1359  switch (static_cast<InstructionOpcodes>(Opcode)) {
1360  case Ret: return 0;
1361  case Br: return 0;
1362  case Switch: return 0;
1363  case IndirectBr: return 0;
1364  case Invoke: return 0;
1365  case Resume: return 0;
1366  case Unreachable: return 0;
1367  case Add: return ISD::ADD;
1368  case FAdd: return ISD::FADD;
1369  case Sub: return ISD::SUB;
1370  case FSub: return ISD::FSUB;
1371  case Mul: return ISD::MUL;
1372  case FMul: return ISD::FMUL;
1373  case UDiv: return ISD::UDIV;
1374  case SDiv: return ISD::SDIV;
1375  case FDiv: return ISD::FDIV;
1376  case URem: return ISD::UREM;
1377  case SRem: return ISD::SREM;
1378  case FRem: return ISD::FREM;
1379  case Shl: return ISD::SHL;
1380  case LShr: return ISD::SRL;
1381  case AShr: return ISD::SRA;
1382  case And: return ISD::AND;
1383  case Or: return ISD::OR;
1384  case Xor: return ISD::XOR;
1385  case Alloca: return 0;
1386  case Load: return ISD::LOAD;
1387  case Store: return ISD::STORE;
1388  case GetElementPtr: return 0;
1389  case Fence: return 0;
1390  case AtomicCmpXchg: return 0;
1391  case AtomicRMW: return 0;
1392  case Trunc: return ISD::TRUNCATE;
1393  case ZExt: return ISD::ZERO_EXTEND;
1394  case SExt: return ISD::SIGN_EXTEND;
1395  case FPToUI: return ISD::FP_TO_UINT;
1396  case FPToSI: return ISD::FP_TO_SINT;
1397  case UIToFP: return ISD::UINT_TO_FP;
1398  case SIToFP: return ISD::SINT_TO_FP;
1399  case FPTrunc: return ISD::FP_ROUND;
1400  case FPExt: return ISD::FP_EXTEND;
1401  case PtrToInt: return ISD::BITCAST;
1402  case IntToPtr: return ISD::BITCAST;
1403  case BitCast: return ISD::BITCAST;
1404  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1405  case ICmp: return ISD::SETCC;
1406  case FCmp: return ISD::SETCC;
1407  case PHI: return 0;
1408  case Call: return 0;
1409  case Select: return ISD::SELECT;
1410  case UserOp1: return 0;
1411  case UserOp2: return 0;
1412  case VAArg: return 0;
1414  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1415  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1416  case ExtractValue: return ISD::MERGE_VALUES;
1417  case InsertValue: return ISD::MERGE_VALUES;
1418  case LandingPad: return 0;
1419  }
1420 
1421  llvm_unreachable("Unknown instruction type encountered!");
1422 }
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
static ConstantInt * ExtractElement(Constant *V, Constant *Idx)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
Simple binary floating point operators.
Definition: ISDOpcodes.h:227
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
Definition: APInt.h:1870
APInt Xor(const APInt &LHS, const APInt &RHS)
Bitwise XOR function for APInt.
Definition: APInt.h:1875
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1865
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
bool llvm::TargetLoweringBase::isBigEndian ( ) const
inlineinherited

Definition at line 153 of file TargetLowering.h.

153 { return !IsLittleEndian; }
bool IsLittleEndian
True if this is a little endian target.
bool llvm::TargetLoweringBase::isCondCodeLegal ( ISD::CondCode  CC,
MVT  VT 
) const
inlineinherited

Return true if the specified condition code is legal on this target.

Definition at line 602 of file TargetLowering.h.

602  {
603  return
604  getCondCodeAction(CC, VT) == Legal ||
605  getCondCodeAction(CC, VT) == Custom;
606  }
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
bool TargetLowering::isConstFalseVal ( const SDNode N) const
inherited

Return if the N is a constant or constant vector equal to the false value from getBooleanContents().

Definition at line 1179 of file TargetLowering.cpp.

1179  {
1180  if (!N)
1181  return false;
1182 
1183  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1184  if (!CN) {
1186  if (!BV)
1187  return false;
1188 
1189  BitVector UndefElements;
1190  CN = BV->getConstantSplatNode(&UndefElements);
1191  // Only interested in constant splats, and we don't try to handle undef
1192  // elements in identifying boolean constants.
1193  if (!CN || UndefElements.none())
1194  return false;
1195  }
1196 
1198  return !CN->getAPIntValue()[0];
1199 
1200  return CN->isNullValue();
1201 }
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:152
ConstantSDNode * getConstantSplatNode(BitVector *UndefElements=nullptr) const
Returns the splatted constant or null if this is not a constant splat.
EVT getValueType(unsigned ResNo) const
const APInt & getAPIntValue() const
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
#define N
bool TargetLowering::isConstTrueVal ( const SDNode N) const
inherited

Return if the N is a constant or constant vector equal to the true value from getBooleanContents().

Definition at line 1149 of file TargetLowering.cpp.

1149  {
1150  if (!N)
1151  return false;
1152 
1153  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1154  if (!CN) {
1156  if (!BV)
1157  return false;
1158 
1159  BitVector UndefElements;
1160  CN = BV->getConstantSplatNode(&UndefElements);
1161  // Only interested in constant splats, and we don't try to handle undef
1162  // elements in identifying boolean constants.
1163  if (!CN || UndefElements.none())
1164  return false;
1165  }
1166 
1167  switch (getBooleanContents(N->getValueType(0))) {
1169  return CN->getAPIntValue()[0];
1171  return CN->isOne();
1173  return CN->isAllOnesValue();
1174  }
1175 
1176  llvm_unreachable("Invalid boolean contents");
1177 }
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:152
ConstantSDNode * getConstantSplatNode(BitVector *UndefElements=nullptr) const
Returns the splatted constant or null if this is not a constant splat.
bool isAllOnesValue() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
EVT getValueType(unsigned ResNo) const
const APInt & getAPIntValue() const
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
#define N
bool AArch64TargetLowering::isDesirableToCommuteWithShift ( const SDNode N) const
overridevirtual

Returns false if N is a bit extraction pattern of (X >> C) & Mask.

Reimplemented from llvm::TargetLowering.

Definition at line 6309 of file AArch64ISelLowering.cpp.

6309  {
6310  EVT VT = N->getValueType(0);
6311  // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6312  // it with shift to let it be lowered to UBFX.
6313  if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6314  isa<ConstantSDNode>(N->getOperand(1))) {
6315  uint64_t TruncMask = N->getConstantOperandVal(1);
6316  if (isMask_64(TruncMask) &&
6317  N->getOperand(0).getOpcode() == ISD::SRL &&
6318  isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6319  return false;
6320  }
6321  return true;
6322 }
unsigned getOpcode() const
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
bool isMask_64(uint64_t Value)
Definition: MathExtras.h:344
unsigned getOpcode() const
uint64_t getConstantOperandVal(unsigned Num) const
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
virtual bool llvm::TargetLowering::IsDesirableToPromoteOp ( SDValue  ,
EVT  
) const
inlinevirtualinherited

This method query the target whether it is beneficial for dag combiner to promote the specified node. If true, it should return the desired promotion type by reference.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2084 of file TargetLowering.h.

2084  {
2085  return false;
2086  }
virtual bool llvm::TargetLowering::isDesirableToTransformToIntegerOp ( unsigned  ,
EVT   
) const
inlinevirtualinherited

Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type. e.g. f32 load -> i32 load can be profitable on ARM.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 2076 of file TargetLowering.h.

2077  {
2078  return false;
2079  }
bool AArch64TargetLowering::isEligibleForTailCallOptimization ( SDValue  Callee,
CallingConv::ID  CalleeCC,
bool  isVarArg,
bool  isCalleeStructRet,
bool  isCallerStructRet,
const SmallVectorImpl< ISD::OutputArg > &  Outs,
const SmallVectorImpl< SDValue > &  OutVals,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SelectionDAG DAG 
) const
private

Definition at line 1982 of file AArch64ISelLowering.cpp.

1987  {
1988  // For CallingConv::C this function knows whether the ABI needs
1989  // changing. That's not true for other conventions so they will have to opt in
1990  // manually.
1991  if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1992  return false;
1993 
1994  const MachineFunction &MF = DAG.getMachineFunction();
1995  const Function *CallerF = MF.getFunction();
1996  CallingConv::ID CallerCC = CallerF->getCallingConv();
1997  bool CCMatch = CallerCC == CalleeCC;
1998 
1999  // Byval parameters hand the function a pointer directly into the stack area
2000  // we want to reuse during a tail call. Working around this *is* possible (see
2001  // X86) but less efficient and uglier in LowerCall.
2002  for (Function::const_arg_iterator i = CallerF->arg_begin(),
2003  e = CallerF->arg_end();
2004  i != e; ++i)
2005  if (i->hasByValAttr())
2006  return false;
2007 
2009  if (IsTailCallConvention(CalleeCC) && CCMatch)
2010  return true;
2011  return false;
2012  }
2013 
2014  // Now we search for cases where we can use a tail call without changing the
2015  // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2016  // concept.
2017 
2018  // I want anyone implementing a new calling convention to think long and hard
2019  // about this assert.
2020  assert((!isVarArg || CalleeCC == CallingConv::C) &&
2021  "Unexpected variadic calling convention");
2022 
2023  if (isVarArg && !Outs.empty()) {
2024  // At least two cases here: if caller is fastcc then we can't have any
2025  // memory arguments (we'd be expected to clean up the stack afterwards). If
2026  // caller is C then we could potentially use its argument area.
2027 
2028  // FIXME: for now we take the most conservative of these in both cases:
2029  // disallow all variadic memory operands.
2031  CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2032  getTargetMachine(), ArgLocs, *DAG.getContext());
2033 
2034  CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2035  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2036  if (!ArgLocs[i].isRegLoc())
2037  return false;
2038  }
2039 
2040  // If the calling conventions do not match, then we'd better make sure the
2041  // results are returned in the same way as what the caller expects.
2042  if (!CCMatch) {
2044  CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2045  getTargetMachine(), RVLocs1, *DAG.getContext());
2046  CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2047 
2049  CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2050  getTargetMachine(), RVLocs2, *DAG.getContext());
2051  CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2052 
2053  if (RVLocs1.size() != RVLocs2.size())
2054  return false;
2055  for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2056  if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2057  return false;
2058  if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2059  return false;
2060  if (RVLocs1[i].isRegLoc()) {
2061  if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2062  return false;
2063  } else {
2064  if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2065  return false;
2066  }
2067  }
2068  }
2069 
2070  // Nothing more to check if the callee is taking no arguments
2071  if (Outs.empty())
2072  return true;
2073 
2075  CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2076  getTargetMachine(), ArgLocs, *DAG.getContext());
2077 
2078  CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2079 
2080  const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2081 
2082  // If the stack arguments for this call would fit into our own save area then
2083  // the call can be made tail.
2084  return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2085 }
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
const TargetMachine & getTargetMachine() const
arg_iterator arg_end()
Definition: Function.h:425
const Function * getFunction() const
CallingConv::ID getCallingConv() const
Definition: Function.h:161
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
ID
LLVM Calling Convention Representation.
Definition: CallingConv.h:26
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
assert(Globals.size() > 1)
unsigned GuaranteedTailCallOpt
arg_iterator arg_begin()
Definition: Function.h:417
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
bool IsTailCallConvention(CallingConv::ID CallCC) const
virtual bool llvm::TargetLoweringBase::isFAbsFree ( EVT  VT) const
inlinevirtualinherited

Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 1382 of file TargetLowering.h.

1382  {
1383  assert(VT.isFloatingPoint());
1384  return false;
1385  }
assert(Globals.size() > 1)
bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd ( EVT  VT) const
overridevirtual

isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd instructions. fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 6280 of file AArch64ISelLowering.cpp.

6280  {
6281  VT = VT.getScalarType();
6282 
6283  if (!VT.isSimple())
6284  return false;
6285 
6286  switch (VT.getSimpleVT().SimpleTy) {
6287  case MVT::f32:
6288  case MVT::f64:
6289  return true;
6290  default:
6291  break;
6292  }
6293 
6294  return false;
6295 }
SimpleValueType SimpleTy
EVT getScalarType() const
Definition: ValueTypes.h:211
bool isSimple() const
Definition: ValueTypes.h:95
MVT getSimpleVT() const
Definition: ValueTypes.h:204
virtual bool llvm::TargetLoweringBase::isFNegFree ( EVT  VT) const
inlinevirtualinherited

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 1375 of file TargetLowering.h.

1375  {
1376  assert(VT.isFloatingPoint());
1377  return false;
1378  }
assert(Globals.size() > 1)
bool AArch64TargetLowering::isFPImmLegal ( const APFloat Imm,
EVT  VT 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 3809 of file AArch64ISelLowering.cpp.

3809  {
3810  // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
3811  // FIXME: We should be able to handle f128 as well with a clever lowering.
3812  if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
3813  return true;
3814 
3815  if (VT == MVT::f64)
3816  return AArch64_AM::getFP64Imm(Imm) != -1;
3817  else if (VT == MVT::f32)
3818  return AArch64_AM::getFP32Imm(Imm) != -1;
3819  return false;
3820 }
static int getFP32Imm(const APInt &Imm)
static int getFP64Imm(const APInt &Imm)
bool isPosZero() const
Definition: APFloat.h:401
bool TargetLowering::isGAPlusOffset ( SDNode N,
const GlobalValue *&  GA,
int64_t &  Offset 
) const
virtualinherited

Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.

isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2005 of file TargetLowering.cpp.

2006  {
2007  if (isa<GlobalAddressSDNode>(N)) {
2008  GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2009  GA = GASD->getGlobal();
2010  Offset += GASD->getOffset();
2011  return true;
2012  }
2013 
2014  if (N->getOpcode() == ISD::ADD) {
2015  SDValue N1 = N->getOperand(0);
2016  SDValue N2 = N->getOperand(1);
2017  if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2019  if (V) {
2020  Offset += V->getSExtValue();
2021  return true;
2022  }
2023  } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2025  if (V) {
2026  Offset += V->getSExtValue();
2027  return true;
2028  }
2029  }
2030  }
2031 
2032  return false;
2033 }
const GlobalValue * getGlobal() const
unsigned getOpcode() const
const SDValue & getOperand(unsigned Num) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDNode * getNode() const
get the SDNode which holds the desired result
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
int64_t getSExtValue() const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
#define N
bool llvm::TargetLoweringBase::isIndexedLoadLegal ( unsigned  IdxMode,
EVT  VT 
) const
inlineinherited

Return true if the specified indexed load is legal on this target.

Definition at line 561 of file TargetLowering.h.

561  {
562  return VT.isSimple() &&
563  (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
564  getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
565  }
LegalizeAction getIndexedLoadAction(unsigned IdxMode, MVT VT) const
bool llvm::TargetLoweringBase::isIndexedStoreLegal ( unsigned  IdxMode,
EVT  VT 
) const
inlineinherited

Return true if the specified indexed load is legal on this target.

Definition at line 579 of file TargetLowering.h.

579  {
580  return VT.isSimple() &&
581  (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
582  getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
583  }
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
bool TargetLowering::isInTailCallPosition ( SelectionDAG DAG,
SDNode Node,
SDValue Chain 
) const
inherited

Check whether a given call node is in tail position within its function. If so, it sets Chain to the input chain of the tail call.

Definition at line 48 of file TargetLowering.cpp.

49  {
50  const Function *F = DAG.getMachineFunction().getFunction();
51 
52  // Conservatively require the attributes of the call to match those of
53  // the return. Ignore noalias because it doesn't affect the call sequence.
54  AttributeSet CallerAttrs = F->getAttributes();
55  if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
56  .removeAttribute(Attribute::NoAlias).hasAttributes())
57  return false;
58 
59  // It's not safe to eliminate the sign / zero extension of the return value.
62  return false;
63 
64  // Check if the only use is a function return node.
65  return isUsedByReturnOnly(Node, Chain);
66 }
Sign extended before/after call.
Definition: Attributes.h:101
F(f)
const Function * getFunction() const
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:872
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const
Considered to not alias after call.
Definition: Attributes.h:82
Zero extended before/after call.
Definition: Attributes.h:114
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:170
bool llvm::TargetLoweringBase::isIntDivCheap ( ) const
inlineinherited

Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.

Definition at line 215 of file TargetLowering.h.

215 { return IntDivIsCheap; }
bool llvm::TargetLoweringBase::isJumpExpensive ( ) const
inlineinherited

Return true if Flow Control is an expensive operation that should be avoided.

Definition at line 231 of file TargetLowering.h.

231 { return JumpIsExpensive; }
bool AArch64TargetLowering::isLegalAddImmediate ( int64_t  Immed) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 6197 of file AArch64ISelLowering.cpp.

6197  {
6198  if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6199  return true;
6200  return false;
6201 }
bool AArch64TargetLowering::isLegalAddressingMode ( const AddrMode AM,
Type Ty 
) const
overridevirtual

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 6213 of file AArch64ISelLowering.cpp.

6214  {
6215  // AArch64 has five basic addressing modes:
6216  // reg
6217  // reg + 9-bit signed offset
6218  // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6219  // reg1 + reg2
6220  // reg + SIZE_IN_BYTES * reg
6221 
6222  // No global is ever allowed as a base.
6223  if (AM.BaseGV)
6224  return false;
6225 
6226  // No reg+reg+imm addressing.
6227  if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6228  return false;
6229 
6230  // check reg + imm case:
6231  // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6232  uint64_t NumBytes = 0;
6233  if (Ty->isSized()) {
6234  uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6235  NumBytes = NumBits / 8;
6236  if (!isPowerOf2_64(NumBits))
6237  NumBytes = 0;
6238  }
6239 
6240  if (!AM.Scale) {
6241  int64_t Offset = AM.BaseOffs;
6242 
6243  // 9-bit signed offset
6244  if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6245  return true;
6246 
6247  // 12-bit unsigned offset
6248  unsigned shift = Log2_64(NumBytes);
6249  if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6250  // Must be a multiple of NumBytes (NumBytes is a power of 2)
6251  (Offset >> shift) << shift == Offset)
6252  return true;
6253  return false;
6254  }
6255 
6256  // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6257 
6258  if (!AM.Scale || AM.Scale == 1 ||
6259  (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6260  return true;
6261  return false;
6262 }
const DataLayout * getDataLayout() const
bool isSized(SmallPtrSet< const Type *, 4 > *Visited=nullptr) const
Definition: Type.h:268
bool isPowerOf2_64(uint64_t Value)
Definition: MathExtras.h:369
uint64_t getTypeSizeInBits(Type *Ty) const
Definition: DataLayout.h:522
unsigned Log2_64(uint64_t Value)
Definition: MathExtras.h:458
bool AArch64TargetLowering::isLegalICmpImmediate ( int64_t  Immed) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 6205 of file AArch64ISelLowering.cpp.

6205  {
6206  if (Immed < 0)
6207  Immed *= -1;
6208  return isLegalAddImmediate(Immed);
6209 }
bool isLegalAddImmediate(int64_t) const override
bool TargetLoweringBase::isLegalRC ( const TargetRegisterClass RC) const
protectedinherited

Return true if the value types that can be represented by the specified register class are all legal.

isLegalRC - Return true if the value types that can be represented by the specified register class are all legal.

Definition at line 934 of file TargetLoweringBase.cpp.

934  {
935  for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
936  I != E; ++I) {
937  if (isTypeLegal(*I))
938  return true;
939  }
940  return false;
941 }
vt_iterator vt_end() const
bool isTypeLegal(EVT VT) const
#define I(x, y, z)
Definition: MD5.cpp:54
vt_iterator vt_begin() const
bool llvm::TargetLoweringBase::isLittleEndian ( ) const
inlineinherited

Definition at line 154 of file TargetLowering.h.

154 { return IsLittleEndian; }
bool IsLittleEndian
True if this is a little endian target.
virtual bool llvm::TargetLoweringBase::isLoadBitCastBeneficial ( EVT  ,
EVT   
) const
inlinevirtualinherited

isLoadBitCastBeneficial() - Return true if the following transform is beneficial. fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 246 of file TargetLowering.h.

246  {
247  return true;
248  }
bool llvm::TargetLoweringBase::isLoadExtLegal ( unsigned  ExtType,
EVT  VT 
) const
inlineinherited

Return true if the specified load with extension is legal on this target.

Definition at line 527 of file TargetLowering.h.

527  {
528  return VT.isSimple() &&
529  getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
530  }
LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const
bool llvm::TargetLoweringBase::isMaskAndBranchFoldingLegal ( ) const
inlineinherited

Return if the target supports combining a chain like:

%andResult = and %val1, #imm-with-one-bit-set;
%icmpResult = icmp %andResult, 0
br i1 %icmpResult, label %dest1, label %dest2

into a single machine instruction of a form like:

brOnBitSet %register, #bitNumber, dest

Definition at line 261 of file TargetLowering.h.

261  {
263  }
virtual bool llvm::TargetLoweringBase::isNarrowingProfitable ( EVT  ,
EVT   
) const
inlinevirtualinherited

Return true if it's profitable to narrow operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.

Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 1402 of file TargetLowering.h.

1402  {
1403  return false;
1404  }
bool llvm::AArch64TargetLowering::isNoopAddrSpaceCast ( unsigned  SrcAS,
unsigned  DestAS 
) const
inlineoverridevirtual

Returns true if a cast between SrcAS and DestAS is a noop.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 242 of file AArch64ISelLowering.h.

242  {
243  // Addrspacecasts are always noops.
244  return true;
245  }
bool AArch64TargetLowering::isOffsetFoldingLegal ( const GlobalAddressSDNode GA) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 3803 of file AArch64ISelLowering.cpp.

3804  {
3805  // The AArch64 target doesn't support folding offsets into global addresses.
3806  return false;
3807 }
bool llvm::TargetLoweringBase::isOperationExpand ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. This is used to help guide high-level lowering decisions.

Definition at line 507 of file TargetLowering.h.

507  {
508  return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
509  }
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
bool isTypeLegal(EVT VT) const
bool llvm::TargetLoweringBase::isOperationLegal ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return true if the specified operation is legal on this target.

Definition at line 512 of file TargetLowering.h.

512  {
513  return (VT == MVT::Other || isTypeLegal(VT)) &&
514  getOperationAction(Op, VT) == Legal;
515  }
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
bool isTypeLegal(EVT VT) const
bool llvm::TargetLoweringBase::isOperationLegalOrCustom ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return true if the specified operation is legal on this target or can be made legal with custom lowering. This is used to help guide high-level lowering decisions.

Definition at line 489 of file TargetLowering.h.

489  {
490  return (VT == MVT::Other || isTypeLegal(VT)) &&
491  (getOperationAction(Op, VT) == Legal ||
492  getOperationAction(Op, VT) == Custom);
493  }
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
bool isTypeLegal(EVT VT) const
bool llvm::TargetLoweringBase::isOperationLegalOrPromote ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return true if the specified operation is legal on this target or can be made legal using promotion. This is used to help guide high-level lowering decisions.

Definition at line 498 of file TargetLowering.h.

498  {
499  return (VT == MVT::Other || isTypeLegal(VT)) &&
500  (getOperationAction(Op, VT) == Legal ||
501  getOperationAction(Op, VT) == Promote);
502  }
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
bool isTypeLegal(EVT VT) const
bool llvm::TargetLoweringBase::isPow2DivCheap ( ) const
inlineinherited

Return true if pow2 div is cheaper than a chain of srl/add/sra.

Definition at line 227 of file TargetLowering.h.

227 { return Pow2DivIsCheap; }
bool llvm::TargetLoweringBase::isPredictableSelectExpensive ( ) const
inlineinherited

Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.

Definition at line 235 of file TargetLowering.h.

235  {
237  }
virtual bool llvm::TargetLoweringBase::isSafeMemOpType ( MVT  ) const
inlinevirtualinherited

Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.

This is mostly true for all types except for some special cases. For example, on X86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.

Reimplemented in llvm::X86TargetLowering.

Definition at line 814 of file TargetLowering.h.

814 { return true; }
bool llvm::TargetLoweringBase::isSelectExpensive ( ) const
inlineinherited

Return true if the select operation is expensive for this target.

Definition at line 174 of file TargetLowering.h.

174 { return SelectIsExpensive; }
virtual bool llvm::TargetLoweringBase::isSelectSupported ( SelectSupportKind  ) const
inlinevirtualinherited

Reimplemented in llvm::ARMTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 176 of file TargetLowering.h.

176  {
177  return true;
178  }
bool AArch64TargetLowering::isShuffleMaskLegal ( const SmallVectorImpl< int > &  M,
EVT  VT 
) const
overridevirtual

isShuffleMaskLegal - Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 5714 of file AArch64ISelLowering.cpp.

5715  {
5716  if (VT.getVectorNumElements() == 4 &&
5717  (VT.is128BitVector() || VT.is64BitVector())) {
5718  unsigned PFIndexes[4];
5719  for (unsigned i = 0; i != 4; ++i) {
5720  if (M[i] < 0)
5721  PFIndexes[i] = 8;
5722  else
5723  PFIndexes[i] = M[i];
5724  }
5725 
5726  // Compute the index in the perfect shuffle table.
5727  unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5728  PFIndexes[2] * 9 + PFIndexes[3];
5729  unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5730  unsigned Cost = (PFEntry >> 30);
5731 
5732  if (Cost <= 4)
5733  return true;
5734  }
5735 
5736  bool DummyBool;
5737  int DummyInt;
5738  unsigned DummyUnsigned;
5739 
5740  return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
5741  isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
5742  isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
5743  // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
5744  isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
5745  isZIPMask(M, VT, DummyUnsigned) ||
5746  isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
5747  isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
5748  isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
5749  isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
5750  isConcatMask(M, VT, VT.getSizeInBits() == 128));
5751 }
static bool isUZP_v_undef_Mask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool isUZPMask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool isTRN_v_undef_Mask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool isINSMask(ArrayRef< int > M, int NumInputElements, bool &DstIsLeft, int &Anomaly)
static bool isZIP_v_undef_Mask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool isTRNMask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static const unsigned PerfectShuffleTable[6561+1]
static bool isEXTMask(ArrayRef< int > M, EVT VT, bool &ReverseEXT, unsigned &Imm)
static bool isREVMask(ArrayRef< int > M, EVT VT, unsigned BlockSize)
static bool isZIPMask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
Definition: ValueTypes.h:136
static bool isConcatMask(ArrayRef< int > Mask, EVT VT, bool SplitLHS)
bool is64BitVector() const
is64BitVector - Return true if this is a 64-bit vector type.
Definition: ValueTypes.h:131
static bool isSplatMask(const int *Mask, EVT VT)
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
bool llvm::TargetLoweringBase::isSlowDivBypassed ( ) const
inlineinherited

Returns true if target has indicated at least one type should be bypassed.

Definition at line 218 of file TargetLowering.h.

218 { return !BypassSlowDivWidths.empty(); }
DenseMap< unsigned int, unsigned int > BypassSlowDivWidths
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: DenseMap.h:68
bool AArch64TargetLowering::IsTailCallConvention ( CallingConv::ID  CallCC) const
private

Definition at line 2125 of file AArch64ISelLowering.cpp.

2125  {
2126  return CallCC == CallingConv::Fast;
2127 }
bool AArch64TargetLowering::isTruncateFree ( Type Ty1,
Type Ty2 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 6102 of file AArch64ISelLowering.cpp.

6102  {
6103  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6104  return false;
6105  unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6106  unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6107  return NumBits1 > NumBits2;
6108 }
bool isIntegerTy() const
Definition: Type.h:193
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
bool AArch64TargetLowering::isTruncateFree ( EVT  VT1,
EVT  VT2 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 6109 of file AArch64ISelLowering.cpp.

6109  {
6110  if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6111  return false;
6112  unsigned NumBits1 = VT1.getSizeInBits();
6113  unsigned NumBits2 = VT2.getSizeInBits();
6114  return NumBits1 > NumBits2;
6115 }
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
bool llvm::TargetLoweringBase::isTruncStoreLegal ( EVT  ValVT,
EVT  MemVT 
) const
inlineinherited

Return true if the specified store with truncation is legal on this target.

Definition at line 544 of file TargetLowering.h.

544  {
545  return isTypeLegal(ValVT) && MemVT.isSimple() &&
546  getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
547  }
LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const
bool isTypeLegal(EVT VT) const
virtual bool llvm::TargetLowering::isTypeDesirableForOp ( unsigned  ,
EVT  VT 
) const
inlinevirtualinherited

Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2068 of file TargetLowering.h.

2068  {
2069  // By default, assume all legal types are desirable.
2070  return isTypeLegal(VT);
2071  }
bool isTypeLegal(EVT VT) const
bool llvm::TargetLoweringBase::isTypeLegal ( EVT  VT) const
inlineinherited

Return true if the target has native support for the specified value type. This means that it has a register that directly holds it without promotions or expansions.

Definition at line 341 of file TargetLowering.h.

341  {
342  assert(!VT.isSimple() ||
343  (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
344  return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
345  }
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
bool AArch64TargetLowering::isUsedByReturnOnly ( SDNode N,
SDValue Chain 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 7856 of file AArch64ISelLowering.cpp.

7857  {
7858  if (N->getNumValues() != 1)
7859  return false;
7860  if (!N->hasNUsesOfValue(1, 0))
7861  return false;
7862 
7863  SDValue TCChain = Chain;
7864  SDNode *Copy = *N->use_begin();
7865  if (Copy->getOpcode() == ISD::CopyToReg) {
7866  // If the copy has a glue operand, we conservatively assume it isn't safe to
7867  // perform a tail call.
7868  if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
7869  MVT::Glue)
7870  return false;
7871  TCChain = Copy->getOperand(0);
7872  } else if (Copy->getOpcode() != ISD::FP_EXTEND)
7873  return false;
7874 
7875  bool HasRet = false;
7876  for (SDNode *Node : Copy->uses()) {
7877  if (Node->getOpcode() != AArch64ISD::RET_FLAG)
7878  return false;
7879  HasRet = true;
7880  }
7881 
7882  if (!HasRet)
7883  return false;
7884 
7885  Chain = TCChain;
7886  return true;
7887 }
bool hasNUsesOfValue(unsigned NUses, unsigned Value) const
unsigned getOpcode() const
unsigned getNumOperands() const
const SDValue & getOperand(unsigned Num) const
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
unsigned getNumValues() const
const DomTreeNodeT * Node
use_iterator use_begin() const
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
iterator_range< use_iterator > uses()
virtual bool llvm::TargetLoweringBase::isVectorClearMaskLegal ( const SmallVectorImpl< int > &  ,
EVT   
) const
inlinevirtualinherited

Similar to isShuffleMaskLegal. This is used by Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.

Reimplemented in llvm::X86TargetLowering.

Definition at line 469 of file TargetLowering.h.

470  {
471  return false;
472  }
virtual bool llvm::TargetLoweringBase::isVectorShiftByScalarCheap ( Type Ty) const
inlinevirtualinherited

Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. On x86, for example, there is a "psllw" instruction for the former case, but no simple instruction for a general "a << b" operation on vectors.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1295 of file TargetLowering.h.

1295  {
1296  return false;
1297  }
bool AArch64TargetLowering::isZExtFree ( Type Ty1,
Type Ty2 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 6119 of file AArch64ISelLowering.cpp.

6119  {
6120  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6121  return false;
6122  unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6123  unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6124  return NumBits1 == 32 && NumBits2 == 64;
6125 }
bool isIntegerTy() const
Definition: Type.h:193
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
bool AArch64TargetLowering::isZExtFree ( EVT  VT1,
EVT  VT2 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 6126 of file AArch64ISelLowering.cpp.

6126  {
6127  if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6128  return false;
6129  unsigned NumBits1 = VT1.getSizeInBits();
6130  unsigned NumBits2 = VT2.getSizeInBits();
6131  return NumBits1 == 32 && NumBits2 == 64;
6132 }
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
bool AArch64TargetLowering::isZExtFree ( SDValue  Val,
EVT  VT2 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 6134 of file AArch64ISelLowering.cpp.

6134  {
6135  EVT VT1 = Val.getValueType();
6136  if (isZExtFree(VT1, VT2)) {
6137  return true;
6138  }
6139 
6140  if (Val.getOpcode() != ISD::LOAD)
6141  return false;
6142 
6143  // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6144  return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6145  VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6146  VT1.getSizeInBits() <= 32);
6147 }
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
bool isZExtFree(Type *Ty1, Type *Ty2) const override
unsigned getOpcode() const
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
bool isSimple() const
Definition: ValueTypes.h:95
SDValue AArch64TargetLowering::LowerAAPCS_VASTART ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3517 of file AArch64ISelLowering.cpp.

3518  {
3519  // The layout of the va_list struct is specified in the AArch64 Procedure Call
3520  // Standard, section B.3.
3521  MachineFunction &MF = DAG.getMachineFunction();
3523  SDLoc DL(Op);
3524 
3525  SDValue Chain = Op.getOperand(0);
3526  SDValue VAList = Op.getOperand(1);
3527  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3528  SmallVector<SDValue, 4> MemOps;
3529 
3530  // void *__stack at offset 0
3531  SDValue Stack =
3532  DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3533  MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3534  MachinePointerInfo(SV), false, false, 8));
3535 
3536  // void *__gr_top at offset 8
3537  int GPRSize = FuncInfo->getVarArgsGPRSize();
3538  if (GPRSize > 0) {
3539  SDValue GRTop, GRTopAddr;
3540 
3541  GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3542  DAG.getConstant(8, getPointerTy()));
3543 
3544  GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3545  GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3546  DAG.getConstant(GPRSize, getPointerTy()));
3547 
3548  MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3549  MachinePointerInfo(SV, 8), false, false, 8));
3550  }
3551 
3552  // void *__vr_top at offset 16
3553  int FPRSize = FuncInfo->getVarArgsFPRSize();
3554  if (FPRSize > 0) {
3555  SDValue VRTop, VRTopAddr;
3556  VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3557  DAG.getConstant(16, getPointerTy()));
3558 
3559  VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3560  VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3561  DAG.getConstant(FPRSize, getPointerTy()));
3562 
3563  MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3564  MachinePointerInfo(SV, 16), false, false, 8));
3565  }
3566 
3567  // int __gr_offs at offset 24
3568  SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3569  DAG.getConstant(24, getPointerTy()));
3570  MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3571  GROffsAddr, MachinePointerInfo(SV, 24), false,
3572  false, 4));
3573 
3574  // int __vr_offs at offset 28
3575  SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3576  DAG.getConstant(28, getPointerTy()));
3577  MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3578  VROffsAddr, MachinePointerInfo(SV, 28), false,
3579  false, 4));
3580 
3581  return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3582 }
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
const DataLayout * DL
True if this is a little endian target.
virtual MVT getPointerTy(uint32_t=0) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
const SDValue & getOperand(unsigned i) const
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
LLVM Value Representation.
Definition: Value.h:69
void AArch64TargetLowering::LowerAsmOperandForConstraint ( SDValue  Op,
std::string &  Constraint,
std::vector< SDValue > &  Ops,
SelectionDAG DAG 
) const
overrideprivatevirtual

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops.

Reimplemented from llvm::TargetLowering.

Definition at line 3962 of file AArch64ISelLowering.cpp.

3964  {
3965  SDValue Result;
3966 
3967  // Currently only support length 1 constraints.
3968  if (Constraint.length() != 1)
3969  return;
3970 
3971  char ConstraintLetter = Constraint[0];
3972  switch (ConstraintLetter) {
3973  default:
3974  break;
3975 
3976  // This set of constraints deal with valid constants for various instructions.
3977  // Validate and return a target constant for them if we can.
3978  case 'z': {
3979  // 'z' maps to xzr or wzr so it needs an input of 0.
3981  if (!C || C->getZExtValue() != 0)
3982  return;
3983 
3984  if (Op.getValueType() == MVT::i64)
3985  Result = DAG.getRegister(AArch64::XZR, MVT::i64);
3986  else
3987  Result = DAG.getRegister(AArch64::WZR, MVT::i32);
3988  break;
3989  }
3990 
3991  case 'I':
3992  case 'J':
3993  case 'K':
3994  case 'L':
3995  case 'M':
3996  case 'N':
3998  if (!C)
3999  return;
4000 
4001  // Grab the value and do some validation.
4002  uint64_t CVal = C->getZExtValue();
4003  switch (ConstraintLetter) {
4004  // The I constraint applies only to simple ADD or SUB immediate operands:
4005  // i.e. 0 to 4095 with optional shift by 12
4006  // The J constraint applies only to ADD or SUB immediates that would be
4007  // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4008  // instruction [or vice versa], in other words -1 to -4095 with optional
4009  // left shift by 12.
4010  case 'I':
4011  if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4012  break;
4013  return;
4014  case 'J': {
4015  uint64_t NVal = -C->getSExtValue();
4016  if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal))
4017  break;
4018  return;
4019  }
4020  // The K and L constraints apply *only* to logical immediates, including
4021  // what used to be the MOVI alias for ORR (though the MOVI alias has now
4022  // been removed and MOV should be used). So these constraints have to
4023  // distinguish between bit patterns that are valid 32-bit or 64-bit
4024  // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4025  // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4026  // versa.
4027  case 'K':
4028  if (AArch64_AM::isLogicalImmediate(CVal, 32))
4029  break;
4030  return;
4031  case 'L':
4032  if (AArch64_AM::isLogicalImmediate(CVal, 64))
4033  break;
4034  return;
4035  // The M and N constraints are a superset of K and L respectively, for use
4036  // with the MOV (immediate) alias. As well as the logical immediates they
4037  // also match 32 or 64-bit immediates that can be loaded either using a
4038  // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4039  // (M) or 64-bit 0x1234000000000000 (N) etc.
4040  // As a note some of this code is liberally stolen from the asm parser.
4041  case 'M': {
4042  if (!isUInt<32>(CVal))
4043  return;
4044  if (AArch64_AM::isLogicalImmediate(CVal, 32))
4045  break;
4046  if ((CVal & 0xFFFF) == CVal)
4047  break;
4048  if ((CVal & 0xFFFF0000ULL) == CVal)
4049  break;
4050  uint64_t NCVal = ~(uint32_t)CVal;
4051  if ((NCVal & 0xFFFFULL) == NCVal)
4052  break;
4053  if ((NCVal & 0xFFFF0000ULL) == NCVal)
4054  break;
4055  return;
4056  }
4057  case 'N': {
4058  if (AArch64_AM::isLogicalImmediate(CVal, 64))
4059  break;
4060  if ((CVal & 0xFFFFULL) == CVal)
4061  break;
4062  if ((CVal & 0xFFFF0000ULL) == CVal)
4063  break;
4064  if ((CVal & 0xFFFF00000000ULL) == CVal)
4065  break;
4066  if ((CVal & 0xFFFF000000000000ULL) == CVal)
4067  break;
4068  uint64_t NCVal = ~CVal;
4069  if ((NCVal & 0xFFFFULL) == NCVal)
4070  break;
4071  if ((NCVal & 0xFFFF0000ULL) == NCVal)
4072  break;
4073  if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4074  break;
4075  if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4076  break;
4077  return;
4078  }
4079  default:
4080  return;
4081  }
4082 
4083  // All assembler immediates are 64-bit integers.
4084  Result = DAG.getTargetConstant(CVal, MVT::i64);
4085  break;
4086  }
4087 
4088  if (Result.getNode()) {
4089  Ops.push_back(Result);
4090  return;
4091  }
4092 
4093  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4094 }
static bool isLogicalImmediate(uint64_t imm, unsigned regSize)
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:406
bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:311
int64_t getSExtValue() const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
EVT getValueType() const
SDValue getRegister(unsigned Reg, EVT VT)
uint64_t getZExtValue() const
SDValue AArch64TargetLowering::LowerBlockAddress ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3481 of file AArch64ISelLowering.cpp.

3482  {
3483  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3484  EVT PtrVT = getPointerTy();
3485  SDLoc DL(Op);
3486  if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3487  !Subtarget->isTargetMachO()) {
3488  const unsigned char MO_NC = AArch64II::MO_NC;
3489  return DAG.getNode(
3490  AArch64ISD::WrapperLarge, DL, PtrVT,
3491  DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3492  DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3493  DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3494  DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3495  } else {
3496  SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3499  SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3500  return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3501  }
3502 }
const TargetMachine & getTargetMachine() const
const AArch64Subtarget * Subtarget
const DataLayout * DL
True if this is a little endian target.
virtual MVT getPointerTy(uint32_t=0) const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:480
SDValue AArch64TargetLowering::LowerBR_CC ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 2853 of file AArch64ISelLowering.cpp.

2853  {
2854  SDValue Chain = Op.getOperand(0);
2855  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2856  SDValue LHS = Op.getOperand(2);
2857  SDValue RHS = Op.getOperand(3);
2858  SDValue Dest = Op.getOperand(4);
2859  SDLoc dl(Op);
2860 
2861  // Handle f128 first, since lowering it will result in comparing the return
2862  // value of a libcall against zero, which is just what the rest of LowerBR_CC
2863  // is expecting to deal with.
2864  if (LHS.getValueType() == MVT::f128) {
2865  softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2866 
2867  // If softenSetCCOperands returned a scalar, we need to compare the result
2868  // against zero to select between true and false values.
2869  if (!RHS.getNode()) {
2870  RHS = DAG.getConstant(0, LHS.getValueType());
2871  CC = ISD::SETNE;
2872  }
2873  }
2874 
2875  // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
2876  // instruction.
2877  unsigned Opc = LHS.getOpcode();
2878  if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
2879  cast<ConstantSDNode>(RHS)->isOne() &&
2880  (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
2881  Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
2882  assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
2883  "Unexpected condition code.");
2884  // Only lower legal XALUO ops.
2885  if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
2886  return SDValue();
2887 
2888  // The actual operation with overflow check.
2889  AArch64CC::CondCode OFCC;
2890  SDValue Value, Overflow;
2891  std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
2892 
2893  if (CC == ISD::SETNE)
2894  OFCC = getInvertedCondCode(OFCC);
2895  SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
2896 
2897  return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest,
2898  CCVal, Overflow);
2899  }
2900 
2901  if (LHS.getValueType().isInteger()) {
2902  assert((LHS.getValueType() == RHS.getValueType()) &&
2903  (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
2904 
2905  // If the RHS of the comparison is zero, we can potentially fold this
2906  // to a specialized branch.
2907  const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
2908  if (RHSC && RHSC->getZExtValue() == 0) {
2909  if (CC == ISD::SETEQ) {
2910  // See if we can use a TBZ to fold in an AND as well.
2911  // TBZ has a smaller branch displacement than CBZ. If the offset is
2912  // out of bounds, a late MI-layer pass rewrites branches.
2913  // 403.gcc is an example that hits this case.
2914  if (LHS.getOpcode() == ISD::AND &&
2915  isa<ConstantSDNode>(LHS.getOperand(1)) &&
2917  SDValue Test = LHS.getOperand(0);
2918  uint64_t Mask = LHS.getConstantOperandVal(1);
2919 
2920  // TBZ only operates on i64's, but the ext should be free.
2921  if (Test.getValueType() == MVT::i32)
2922  Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2923 
2924  return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
2925  DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2926  }
2927 
2928  return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
2929  } else if (CC == ISD::SETNE) {
2930  // See if we can use a TBZ to fold in an AND as well.
2931  // TBZ has a smaller branch displacement than CBZ. If the offset is
2932  // out of bounds, a late MI-layer pass rewrites branches.
2933  // 403.gcc is an example that hits this case.
2934  if (LHS.getOpcode() == ISD::AND &&
2935  isa<ConstantSDNode>(LHS.getOperand(1)) &&
2937  SDValue Test = LHS.getOperand(0);
2938  uint64_t Mask = LHS.getConstantOperandVal(1);
2939 
2940  // TBNZ only operates on i64's, but the ext should be free.
2941  if (Test.getValueType() == MVT::i32)
2942  Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2943 
2944  return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
2945  DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2946  }
2947 
2948  return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
2949  }
2950  }
2951 
2952  SDValue CCVal;
2953  SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
2954  return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
2955  Cmp);
2956  }
2957 
2958  assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2959 
2960  // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
2961  // clean. Some of them require two branches to implement.
2962  SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
2963  AArch64CC::CondCode CC1, CC2;
2964  changeFPCCToAArch64CC(CC, CC1, CC2);
2965  SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
2966  SDValue BR1 =
2967  DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
2968  if (CC2 != AArch64CC::AL) {
2969  SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
2970  return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
2971  Cmp);
2972  }
2973 
2974  return BR1;
2975 }
SDValue getValue(unsigned R) const
static CondCode getInvertedCondCode(CondCode Code)
Same for subtraction.
Definition: ISDOpcodes.h:221
static std::pair< SDValue, SDValue > getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG)
unsigned getResNo() const
get the index which selects a specific result in the SDNode
EVT getValueType(unsigned ResNo) const
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
static int Value(bit_value_t V)
static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl)
SDValue getAnyExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
SDNode * getNode() const
get the SDNode which holds the desired result
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
static void changeFPCCToAArch64CC(ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2)
changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
bool isPowerOf2_64(uint64_t Value)
Definition: MathExtras.h:369
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
uint64_t getConstantOperandVal(unsigned i) const
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
Same for multiplication.
Definition: ISDOpcodes.h:224
static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl, SelectionDAG &DAG)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
unsigned Log2_64(uint64_t Value)
Definition: MathExtras.h:458
uint64_t getZExtValue() const
void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const
SDValue AArch64TargetLowering::LowerBUILD_VECTOR ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5234 of file AArch64ISelLowering.cpp.

5235  {
5236  SDLoc dl(Op);
5237  EVT VT = Op.getValueType();
5238  Op = NormalizeBuildVector(Op, DAG);
5239  BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5240 
5241  APInt CnstBits(VT.getSizeInBits(), 0);
5242  APInt UndefBits(VT.getSizeInBits(), 0);
5243  if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5244  // We make use of a little bit of goto ickiness in order to avoid having to
5245  // duplicate the immediate matching logic for the undef toggled case.
5246  bool SecondTry = false;
5247  AttemptModImm:
5248 
5249  if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5250  CnstBits = CnstBits.zextOrTrunc(64);
5251  uint64_t CnstVal = CnstBits.getZExtValue();
5252 
5253  // Certain magic vector constants (used to express things like NOT
5254  // and NEG) are passed through unmodified. This allows codegen patterns
5255  // for these operations to match. Special-purpose patterns will lower
5256  // these immediates to MOVIs if it proves necessary.
5257  if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5258  return Op;
5259 
5260  // The many faces of MOVI...
5261  if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5262  CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5263  if (VT.getSizeInBits() == 128) {
5265  DAG.getConstant(CnstVal, MVT::i32));
5266  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5267  }
5268 
5269  // Support the V64 version via subregister insertion.
5271  DAG.getConstant(CnstVal, MVT::i32));
5272  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5273  }
5274 
5275  if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5276  CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5277  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5278  SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5279  DAG.getConstant(CnstVal, MVT::i32),
5280  DAG.getConstant(0, MVT::i32));
5281  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5282  }
5283 
5284  if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5285  CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5286  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5287  SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5288  DAG.getConstant(CnstVal, MVT::i32),
5289  DAG.getConstant(8, MVT::i32));
5290  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5291  }
5292 
5293  if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5294  CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5295  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5296  SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5297  DAG.getConstant(CnstVal, MVT::i32),
5298  DAG.getConstant(16, MVT::i32));
5299  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5300  }
5301 
5302  if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5303  CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5304  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5305  SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5306  DAG.getConstant(CnstVal, MVT::i32),
5307  DAG.getConstant(24, MVT::i32));
5308  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5309  }
5310 
5311  if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5312  CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5313  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5314  SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5315  DAG.getConstant(CnstVal, MVT::i32),
5316  DAG.getConstant(0, MVT::i32));
5317  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5318  }
5319 
5320  if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5321  CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5322  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5323  SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5324  DAG.getConstant(CnstVal, MVT::i32),
5325  DAG.getConstant(8, MVT::i32));
5326  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5327  }
5328 
5329  if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5330  CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5331  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5332  SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5333  DAG.getConstant(CnstVal, MVT::i32),
5334  DAG.getConstant(264, MVT::i32));
5335  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5336  }
5337 
5338  if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5339  CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5340  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5341  SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5342  DAG.getConstant(CnstVal, MVT::i32),
5343  DAG.getConstant(272, MVT::i32));
5344  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5345  }
5346 
5347  if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5348  CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5349  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5350  SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5351  DAG.getConstant(CnstVal, MVT::i32));
5352  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5353  }
5354 
5355  // The few faces of FMOV...
5356  if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5357  CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5358  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5359  SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5360  DAG.getConstant(CnstVal, MVT::i32));
5361  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5362  }
5363 
5364  if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5365  VT.getSizeInBits() == 128) {
5366  CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5367  SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5368  DAG.getConstant(CnstVal, MVT::i32));
5369  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5370  }
5371 
5372  // The many faces of MVNI...
5373  CnstVal = ~CnstVal;
5374  if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5375  CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5376  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5377  SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5378  DAG.getConstant(CnstVal, MVT::i32),
5379  DAG.getConstant(0, MVT::i32));
5380  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5381  }
5382 
5383  if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5384  CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5385  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5386  SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5387  DAG.getConstant(CnstVal, MVT::i32),
5388  DAG.getConstant(8, MVT::i32));
5389  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5390  }
5391 
5392  if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5393  CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5394  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5395  SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5396  DAG.getConstant(CnstVal, MVT::i32),
5397  DAG.getConstant(16, MVT::i32));
5398  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5399  }
5400 
5401  if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5402  CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5403  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5404  SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5405  DAG.getConstant(CnstVal, MVT::i32),
5406  DAG.getConstant(24, MVT::i32));
5407  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5408  }
5409 
5410  if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5411  CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5412  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5413  SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5414  DAG.getConstant(CnstVal, MVT::i32),
5415  DAG.getConstant(0, MVT::i32));
5416  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5417  }
5418 
5419  if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5420  CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5421  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5422  SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5423  DAG.getConstant(CnstVal, MVT::i32),
5424  DAG.getConstant(8, MVT::i32));
5425  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5426  }
5427 
5428  if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5429  CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5430  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5431  SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5432  DAG.getConstant(CnstVal, MVT::i32),
5433  DAG.getConstant(264, MVT::i32));
5434  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5435  }
5436 
5437  if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5438  CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5439  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5440  SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5441  DAG.getConstant(CnstVal, MVT::i32),
5442  DAG.getConstant(272, MVT::i32));
5443  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5444  }
5445  }
5446 
5447  if (SecondTry)
5448  goto FailedModImm;
5449  SecondTry = true;
5450  CnstBits = UndefBits;
5451  goto AttemptModImm;
5452  }
5453 FailedModImm:
5454 
5455  // Scan through the operands to find some interesting properties we can
5456  // exploit:
5457  // 1) If only one value is used, we can use a DUP, or
5458  // 2) if only the low element is not undef, we can just insert that, or
5459  // 3) if only one constant value is used (w/ some non-constant lanes),
5460  // we can splat the constant value into the whole vector then fill
5461  // in the non-constant lanes.
5462  // 4) FIXME: If different constant values are used, but we can intelligently
5463  // select the values we'll be overwriting for the non-constant
5464  // lanes such that we can directly materialize the vector
5465  // some other way (MOVI, e.g.), we can be sneaky.
5466  unsigned NumElts = VT.getVectorNumElements();
5467  bool isOnlyLowElement = true;
5468  bool usesOnlyOneValue = true;
5469  bool usesOnlyOneConstantValue = true;
5470  bool isConstant = true;
5471  unsigned NumConstantLanes = 0;
5472  SDValue Value;
5473  SDValue ConstantValue;
5474  for (unsigned i = 0; i < NumElts; ++i) {
5475  SDValue V = Op.getOperand(i);
5476  if (V.getOpcode() == ISD::UNDEF)
5477  continue;
5478  if (i > 0)
5479  isOnlyLowElement = false;
5480  if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5481  isConstant = false;
5482 
5483  if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5484  ++NumConstantLanes;
5485  if (!ConstantValue.getNode())
5486  ConstantValue = V;
5487  else if (ConstantValue != V)
5488  usesOnlyOneConstantValue = false;
5489  }
5490 
5491  if (!Value.getNode())
5492  Value = V;
5493  else if (V != Value)
5494  usesOnlyOneValue = false;
5495  }
5496 
5497  if (!Value.getNode())
5498  return DAG.getUNDEF(VT);
5499 
5500  if (isOnlyLowElement)
5501  return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5502 
5503  // Use DUP for non-constant splats. For f32 constant splats, reduce to
5504  // i32 and try again.
5505  if (usesOnlyOneValue) {
5506  if (!isConstant) {
5507  if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5508  Value.getValueType() != VT)
5509  return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5510 
5511  // This is actually a DUPLANExx operation, which keeps everything vectory.
5512 
5513  // DUPLANE works on 128-bit vectors, widen it if necessary.
5514  SDValue Lane = Value.getOperand(1);
5515  Value = Value.getOperand(0);
5516  if (Value.getValueType().getSizeInBits() == 64)
5517  Value = WidenVector(Value, DAG);
5518 
5519  unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5520  return DAG.getNode(Opcode, dl, VT, Value, Lane);
5521  }
5522 
5525  MVT NewType =
5527  for (unsigned i = 0; i < NumElts; ++i)
5528  Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5529  EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5530  SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5531  Val = LowerBUILD_VECTOR(Val, DAG);
5532  if (Val.getNode())
5533  return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5534  }
5535  }
5536 
5537  // If there was only one constant value used and for more than one lane,
5538  // start by splatting that value, then replace the non-constant lanes. This
5539  // is better than the default, which will perform a separate initialization
5540  // for each lane.
5541  if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5542  SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5543  // Now insert the non-constant lanes.
5544  for (unsigned i = 0; i < NumElts; ++i) {
5545  SDValue V = Op.getOperand(i);
5546  SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5547  if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5548  // Note that type legalization likely mucked about with the VT of the
5549  // source operand, so we may have to convert it here before inserting.
5550  Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5551  }
5552  }
5553  return Val;
5554  }
5555 
5556  // If all elements are constants and the case above didn't get hit, fall back
5557  // to the default expansion, which will generate a load from the constant
5558  // pool.
5559  if (isConstant)
5560  return SDValue();
5561 
5562  // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5563  if (NumElts >= 4) {
5564  SDValue shuffle = ReconstructShuffle(Op, DAG);
5565  if (shuffle != SDValue())
5566  return shuffle;
5567  }
5568 
5569  // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5570  // know the default expansion would otherwise fall back on something even
5571  // worse. For a vector with one or two non-undef values, that's
5572  // scalar_to_vector for the elements followed by a shuffle (provided the
5573  // shuffle is valid for the target) and materialization element by element
5574  // on the stack followed by a load for everything else.
5575  if (!isConstant && !usesOnlyOneValue) {
5576  SDValue Vec = DAG.getUNDEF(VT);
5577  SDValue Op0 = Op.getOperand(0);
5578  unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
5579  unsigned i = 0;
5580  // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
5581  // a) Avoid a RMW dependency on the full vector register, and
5582  // b) Allow the register coalescer to fold away the copy if the
5583  // value is already in an S or D register.
5584  if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
5585  unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
5586  MachineSDNode *N =
5587  DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
5588  DAG.getTargetConstant(SubIdx, MVT::i32));
5589  Vec = SDValue(N, 0);
5590  ++i;
5591  }
5592  for (; i < NumElts; ++i) {
5593  SDValue V = Op.getOperand(i);
5594  if (V.getOpcode() == ISD::UNDEF)
5595  continue;
5596  SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5597  Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5598  }
5599  return Vec;
5600  }
5601 
5602  // Just use the default expansion. We failed to find a better alternative.
5603  return SDValue();
5604 }
static bool isAdvSIMDModImmType6(uint64_t Imm)
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
static uint8_t encodeAdvSIMDModImmType3(uint64_t Imm)
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1302
static bool isAdvSIMDModImmType12(uint64_t Imm)
static bool isAdvSIMDModImmType4(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType1(uint64_t Imm)
static SDValue NormalizeBuildVector(SDValue Op, SelectionDAG &DAG)
static unsigned getDUPLANEOp(EVT EltType)
static bool isAdvSIMDModImmType3(uint64_t Imm)
APInt LLVM_ATTRIBUTE_UNUSED_RESULT zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
Definition: APInt.cpp:1003
static bool isAdvSIMDModImmType7(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType6(uint64_t Imm)
static bool isAdvSIMDModImmType5(uint64_t Imm)
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
EVT getVectorElementType() const
Definition: ValueTypes.h:217
SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const
static int Value(bit_value_t V)
static bool isAdvSIMDModImmType2(uint64_t Imm)
SDValue getUNDEF(EVT VT)
getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:625
static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG)
UNDEF - An undefined node.
Definition: ISDOpcodes.h:159
static bool isAdvSIMDModImmType9(uint64_t Imm)
SDNode * getNode() const
get the SDNode which holds the desired result
const SDValue & getOperand(unsigned i) const
static bool isAdvSIMDModImmType1(uint64_t Imm)
unsigned getOpcode() const
static bool isAdvSIMDModImmType8(uint64_t Imm)
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
static uint8_t encodeAdvSIMDModImmType12(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType2(uint64_t Imm)
SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:406
Class for arbitrary precision integers.
Definition: APInt.h:75
static uint8_t encodeAdvSIMDModImmType10(uint64_t Imm)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
static uint8_t encodeAdvSIMDModImmType5(uint64_t Imm)
static bool isAdvSIMDModImmType10(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType8(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType4(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType11(uint64_t Imm)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
#define N
MachineSDNode * getMachineNode(unsigned Opcode, SDLoc dl, EVT VT)
EVT getValueType() const
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
static uint8_t encodeAdvSIMDModImmType9(uint64_t Imm)
static bool isAdvSIMDModImmType11(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType7(uint64_t Imm)
static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits, APInt &UndefBits)
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
SDValue AArch64TargetLowering::LowerCall ( CallLoweringInfo CLI,
SmallVectorImpl< SDValue > &  InVals 
) const
overrideprivatevirtual

LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain, and add input and output parameter nodes.

Reimplemented from llvm::TargetLowering.

Definition at line 2132 of file AArch64ISelLowering.cpp.

2133  {
2134  SelectionDAG &DAG = CLI.DAG;
2135  SDLoc &DL = CLI.DL;
2136  SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2137  SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2139  SDValue Chain = CLI.Chain;
2140  SDValue Callee = CLI.Callee;
2141  bool &IsTailCall = CLI.IsTailCall;
2142  CallingConv::ID CallConv = CLI.CallConv;
2143  bool IsVarArg = CLI.IsVarArg;
2144 
2145  MachineFunction &MF = DAG.getMachineFunction();
2146  bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2147  bool IsThisReturn = false;
2148 
2150  bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2151  bool IsSibCall = false;
2152 
2153  if (IsTailCall) {
2154  // Check if it's really possible to do a tail call.
2155  IsTailCall = isEligibleForTailCallOptimization(
2156  Callee, CallConv, IsVarArg, IsStructRet,
2157  MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2158  if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2159  report_fatal_error("failed to perform tail call elimination on a call "
2160  "site marked musttail");
2161 
2162  // A sibling call is one where we're under the usual C ABI and not planning
2163  // to change that but can still do a tail call:
2164  if (!TailCallOpt && IsTailCall)
2165  IsSibCall = true;
2166 
2167  if (IsTailCall)
2168  ++NumTailCalls;
2169  }
2170 
2171  // Analyze operands of the call, assigning locations to each operand.
2173  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2174  getTargetMachine(), ArgLocs, *DAG.getContext());
2175 
2176  if (IsVarArg) {
2177  // Handle fixed and variable vector arguments differently.
2178  // Variable vector arguments always go into memory.
2179  unsigned NumArgs = Outs.size();
2180 
2181  for (unsigned i = 0; i != NumArgs; ++i) {
2182  MVT ArgVT = Outs[i].VT;
2183  ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2184  CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2185  /*IsVarArg=*/ !Outs[i].IsFixed);
2186  bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2187  assert(!Res && "Call operand has unhandled type");
2188  (void)Res;
2189  }
2190  } else {
2191  // At this point, Outs[].VT may already be promoted to i32. To correctly
2192  // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2193  // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2194  // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2195  // we use a special version of AnalyzeCallOperands to pass in ValVT and
2196  // LocVT.
2197  unsigned NumArgs = Outs.size();
2198  for (unsigned i = 0; i != NumArgs; ++i) {
2199  MVT ValVT = Outs[i].VT;
2200  // Get type of the original argument.
2201  EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2202  /*AllowUnknown*/ true);
2203  MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2204  ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2205  // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2206  if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2207  ValVT = MVT::i8;
2208  else if (ActualMVT == MVT::i16)
2209  ValVT = MVT::i16;
2210 
2211  CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2212  bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2213  assert(!Res && "Call operand has unhandled type");
2214  (void)Res;
2215  }
2216  }
2217 
2218  // Get a count of how many bytes are to be pushed on the stack.
2219  unsigned NumBytes = CCInfo.getNextStackOffset();
2220 
2221  if (IsSibCall) {
2222  // Since we're not changing the ABI to make this a tail call, the memory
2223  // operands are already available in the caller's incoming argument space.
2224  NumBytes = 0;
2225  }
2226 
2227  // FPDiff is the byte offset of the call's argument area from the callee's.
2228  // Stores to callee stack arguments will be placed in FixedStackSlots offset
2229  // by this amount for a tail call. In a sibling call it must be 0 because the
2230  // caller will deallocate the entire stack and the callee still expects its
2231  // arguments to begin at SP+0. Completely unused for non-tail calls.
2232  int FPDiff = 0;
2233 
2234  if (IsTailCall && !IsSibCall) {
2235  unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2236 
2237  // Since callee will pop argument stack as a tail call, we must keep the
2238  // popped size 16-byte aligned.
2239  NumBytes = RoundUpToAlignment(NumBytes, 16);
2240 
2241  // FPDiff will be negative if this tail call requires more space than we
2242  // would automatically have in our incoming argument space. Positive if we
2243  // can actually shrink the stack.
2244  FPDiff = NumReusableBytes - NumBytes;
2245 
2246  // The stack pointer must be 16-byte aligned at all times it's used for a
2247  // memory operation, which in practice means at *all* times and in
2248  // particular across call boundaries. Therefore our own arguments started at
2249  // a 16-byte aligned SP and the delta applied for the tail call should
2250  // satisfy the same constraint.
2251  assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2252  }
2253 
2254  // Adjust the stack pointer for the new arguments...
2255  // These operations are automatically eliminated by the prolog/epilog pass
2256  if (!IsSibCall)
2257  Chain =
2258  DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2259 
2260  SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2261 
2263  SmallVector<SDValue, 8> MemOpChains;
2264 
2265  // Walk the register/memloc assignments, inserting copies/loads.
2266  for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2267  ++i, ++realArgIdx) {
2268  CCValAssign &VA = ArgLocs[i];
2269  SDValue Arg = OutVals[realArgIdx];
2270  ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2271 
2272  // Promote the value if needed.
2273  switch (VA.getLocInfo()) {
2274  default:
2275  llvm_unreachable("Unknown loc info!");
2276  case CCValAssign::Full:
2277  break;
2278  case CCValAssign::SExt:
2279  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2280  break;
2281  case CCValAssign::ZExt:
2282  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2283  break;
2284  case CCValAssign::AExt:
2285  if (Outs[realArgIdx].ArgVT == MVT::i1) {
2286  // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2287  Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2288  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2289  }
2290  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2291  break;
2292  case CCValAssign::BCvt:
2293  Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2294  break;
2295  case CCValAssign::FPExt:
2296  Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2297  break;
2298  }
2299 
2300  if (VA.isRegLoc()) {
2301  if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2302  assert(VA.getLocVT() == MVT::i64 &&
2303  "unexpected calling convention register assignment");
2304  assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2305  "unexpected use of 'returned'");
2306  IsThisReturn = true;
2307  }
2308  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2309  } else {
2310  assert(VA.isMemLoc());
2311 
2312  SDValue DstAddr;
2313  MachinePointerInfo DstInfo;
2314 
2315  // FIXME: This works on big-endian for composite byvals, which are the
2316  // common case. It should also work for fundamental types too.
2317  uint32_t BEAlign = 0;
2318  unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2319  : VA.getLocVT().getSizeInBits();
2320  OpSize = (OpSize + 7) / 8;
2321  if (!Subtarget->isLittleEndian() && !Flags.isByVal()) {
2322  if (OpSize < 8)
2323  BEAlign = 8 - OpSize;
2324  }
2325  unsigned LocMemOffset = VA.getLocMemOffset();
2326  int32_t Offset = LocMemOffset + BEAlign;
2327  SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2328  PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2329 
2330  if (IsTailCall) {
2331  Offset = Offset + FPDiff;
2332  int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2333 
2334  DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2335  DstInfo = MachinePointerInfo::getFixedStack(FI);
2336 
2337  // Make sure any stack arguments overlapping with where we're storing
2338  // are loaded before this eventual operation. Otherwise they'll be
2339  // clobbered.
2340  Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2341  } else {
2342  SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2343 
2344  DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2345  DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2346  }
2347 
2348  if (Outs[i].Flags.isByVal()) {
2349  SDValue SizeNode =
2350  DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2351  SDValue Cpy = DAG.getMemcpy(
2352  Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2353  /*isVolatile = */ false,
2354  /*alwaysInline = */ false, DstInfo, MachinePointerInfo());
2355 
2356  MemOpChains.push_back(Cpy);
2357  } else {
2358  // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2359  // promoted to a legal register type i32, we should truncate Arg back to
2360  // i1/i8/i16.
2361  if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2362  VA.getValVT() == MVT::i16)
2363  Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2364 
2365  SDValue Store =
2366  DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2367  MemOpChains.push_back(Store);
2368  }
2369  }
2370  }
2371 
2372  if (!MemOpChains.empty())
2373  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2374 
2375  // Build a sequence of copy-to-reg nodes chained together with token chain
2376  // and flag operands which copy the outgoing args into the appropriate regs.
2377  SDValue InFlag;
2378  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2379  Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2380  RegsToPass[i].second, InFlag);
2381  InFlag = Chain.getValue(1);
2382  }
2383 
2384  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2385  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2386  // node so that legalize doesn't hack it.
2387  if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2388  Subtarget->isTargetMachO()) {
2389  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2390  const GlobalValue *GV = G->getGlobal();
2391  bool InternalLinkage = GV->hasInternalLinkage();
2392  if (InternalLinkage)
2393  Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2394  else {
2395  Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2397  Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2398  }
2399  } else if (ExternalSymbolSDNode *S =
2400  dyn_cast<ExternalSymbolSDNode>(Callee)) {
2401  const char *Sym = S->getSymbol();
2402  Callee =
2404  Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2405  }
2406  } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2407  const GlobalValue *GV = G->getGlobal();
2408  Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2409  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2410  const char *Sym = S->getSymbol();
2411  Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2412  }
2413 
2414  // We don't usually want to end the call-sequence here because we would tidy
2415  // the frame up *after* the call, however in the ABI-changing tail-call case
2416  // we've carefully laid out the parameters so that when sp is reset they'll be
2417  // in the correct location.
2418  if (IsTailCall && !IsSibCall) {
2419  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2420  DAG.getIntPtrConstant(0, true), InFlag, DL);
2421  InFlag = Chain.getValue(1);
2422  }
2423 
2424  std::vector<SDValue> Ops;
2425  Ops.push_back(Chain);
2426  Ops.push_back(Callee);
2427 
2428  if (IsTailCall) {
2429  // Each tail call may have to adjust the stack by a different amount, so
2430  // this information must travel along with the operation for eventual
2431  // consumption by emitEpilogue.
2432  Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2433  }
2434 
2435  // Add argument registers to the end of the list so that they are known live
2436  // into the call.
2437  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2438  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2439  RegsToPass[i].second.getValueType()));
2440 
2441  // Add a register mask operand representing the call-preserved registers.
2442  const uint32_t *Mask;
2444  const AArch64RegisterInfo *ARI =
2445  static_cast<const AArch64RegisterInfo *>(TRI);
2446  if (IsThisReturn) {
2447  // For 'this' returns, use the X0-preserving mask if applicable
2448  Mask = ARI->getThisReturnPreservedMask(CallConv);
2449  if (!Mask) {
2450  IsThisReturn = false;
2451  Mask = ARI->getCallPreservedMask(CallConv);
2452  }
2453  } else
2454  Mask = ARI->getCallPreservedMask(CallConv);
2455 
2456  assert(Mask && "Missing call preserved mask for calling convention");
2457  Ops.push_back(DAG.getRegisterMask(Mask));
2458 
2459  if (InFlag.getNode())
2460  Ops.push_back(InFlag);
2461 
2462  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2463 
2464  // If we're doing a tall call, use a TC_RETURN here rather than an
2465  // actual call instruction.
2466  if (IsTailCall)
2467  return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2468 
2469  // Returns a chain and a flag for retval copy to use.
2470  Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2471  InFlag = Chain.getValue(1);
2472 
2473  uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2474  ? RoundUpToAlignment(NumBytes, 16)
2475  : 0;
2476 
2477  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2478  DAG.getIntPtrConstant(CalleePopBytes, true),
2479  InFlag, DL);
2480  if (!Ins.empty())
2481  InFlag = Chain.getValue(1);
2482 
2483  // Handle result values, copying them out of physregs into vregs that we
2484  // return.
2485  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2486  InVals, IsThisReturn,
2487  IsThisReturn ? OutVals[0] : SDValue());
2488 }
SDValue getValue(unsigned R) const
MVT getValVT() const
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, SDLoc DL)
Definition: SelectionDAG.h:612
LocInfo getLocInfo() const
const TargetMachine & getTargetMachine() const
unsigned getSizeInBits() const
unsigned getByValSize() const
const Function * getFunction() const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
const uint32_t * getCallPreservedMask(CallingConv::ID) const override
bool isRegLoc() const
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
const AArch64Subtarget * Subtarget
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
bool hasInternalLinkage() const
Definition: GlobalValue.h:259
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:433
SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo *MFI, int ClobberedFI) const
const DataLayout * DL
True if this is a little endian target.
SDVTList getVTList(EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
ID
LLVM Calling Convention Representation.
Definition: CallingConv.h:26
#define G(x, y, z)
Definition: MD5.cpp:52
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL)
Definition: SelectionDAG.h:603
unsigned getLocReg() const
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
SDValue getRegisterMask(const uint32_t *RegMask)
bool hasStructRetAttr() const
Determine if the function returns a structure through first pointer argument.
Definition: Function.h:305
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
MVT getLocVT() const
bool isLittleEndian() const
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
unsigned GuaranteedTailCallOpt
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
const uint32_t * getThisReturnPreservedMask(CallingConv::ID) const
SDValue getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
unsigned getByValAlign() const
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:406
MachineFrameInfo * getFrameInfo()
static MachinePointerInfo getStack(int64_t Offset)
getStack - stack pointer relative access.
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
bool isMemLoc() const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align)
Definition: MathExtras.h:593
bool isEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
const TargetMachine & getTarget() const
virtual const TargetRegisterInfo * getRegisterInfo() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
bool isSimple() const
Definition: ValueTypes.h:95
SDValue getRegister(unsigned Reg, EVT VT)
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, bool isThisReturn, SDValue ThisVal) const
unsigned getLocMemOffset() const
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable)
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const
MVT getSimpleVT() const
Definition: ValueTypes.h:204
SDValue AArch64TargetLowering::LowerCallResult ( SDValue  Chain,
SDValue  InFlag,
CallingConv::ID  CallConv,
bool  isVarArg,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SDLoc  DL,
SelectionDAG DAG,
SmallVectorImpl< SDValue > &  InVals,
bool  isThisReturn,
SDValue  ThisVal 
) const
private

LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate physical registers.

Definition at line 1934 of file AArch64ISelLowering.cpp.

1938  {
1940  ? RetCC_AArch64_WebKit_JS
1941  : RetCC_AArch64_AAPCS;
1942  // Assign locations to each value returned by this call.
1944  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1945  getTargetMachine(), RVLocs, *DAG.getContext());
1946  CCInfo.AnalyzeCallResult(Ins, RetCC);
1947 
1948  // Copy all of the result registers out of their specified physreg.
1949  for (unsigned i = 0; i != RVLocs.size(); ++i) {
1950  CCValAssign VA = RVLocs[i];
1951 
1952  // Pass 'this' value directly from the argument to return value, to avoid
1953  // reg unit interference
1954  if (i == 0 && isThisReturn) {
1955  assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
1956  "unexpected return calling convention register assignment");
1957  InVals.push_back(ThisVal);
1958  continue;
1959  }
1960 
1961  SDValue Val =
1962  DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
1963  Chain = Val.getValue(1);
1964  InFlag = Val.getValue(2);
1965 
1966  switch (VA.getLocInfo()) {
1967  default:
1968  llvm_unreachable("Unknown loc info!");
1969  case CCValAssign::Full:
1970  break;
1971  case CCValAssign::BCvt:
1972  Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
1973  break;
1974  }
1975 
1976  InVals.push_back(Val);
1977  }
1978 
1979  return Chain;
1980 }
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
SDValue getValue(unsigned R) const
MVT getValVT() const
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
LocInfo getLocInfo() const
const TargetMachine & getTargetMachine() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
unsigned getLocReg() const
assert(Globals.size() > 1)
MVT getLocVT() const
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
bool needsCustom() const
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
std::pair< SDValue, SDValue > TargetLowering::LowerCallTo ( TargetLowering::CallLoweringInfo CLI) const
inherited

This function lowers an abstract call to a function into an actual call. This returns a pair of operands. The first element is the return value for the function (if RetTy is not VoidTy). The second element is the outgoing token chain. It calls LowerCall to do the actual lowering.

TargetLowering::LowerCallTo - This is the default LowerCallTo implementation, which just calls LowerCall. FIXME: When all targets are migrated to using LowerCall, this hook should be integrated into SDISel.

Definition at line 7072 of file SelectionDAGBuilder.cpp.

7072  {
7073  // Handle the incoming return values from the call.
7074  CLI.Ins.clear();
7075  Type *OrigRetTy = CLI.RetTy;
7076  SmallVector<EVT, 4> RetTys;
7077  SmallVector<uint64_t, 4> Offsets;
7078  ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7079 
7081  GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7082 
7083  bool CanLowerReturn =
7084  this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7085  CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7086 
7087  SDValue DemoteStackSlot;
7088  int DemoteStackIdx = -100;
7089  if (!CanLowerReturn) {
7090  // FIXME: equivalent assert?
7091  // assert(!CS.hasInAllocaArgument() &&
7092  // "sret demotion is incompatible with inalloca");
7093  uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7094  unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7096  DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7097  Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7098 
7099  DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7100  ArgListEntry Entry;
7101  Entry.Node = DemoteStackSlot;
7102  Entry.Ty = StackSlotPtrType;
7103  Entry.isSExt = false;
7104  Entry.isZExt = false;
7105  Entry.isInReg = false;
7106  Entry.isSRet = true;
7107  Entry.isNest = false;
7108  Entry.isByVal = false;
7109  Entry.isReturned = false;
7110  Entry.Alignment = Align;
7111  CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7112  CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7113  } else {
7114  for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7115  EVT VT = RetTys[I];
7116  MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7117  unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7118  for (unsigned i = 0; i != NumRegs; ++i) {
7120  MyFlags.VT = RegisterVT;
7121  MyFlags.ArgVT = VT;
7122  MyFlags.Used = CLI.IsReturnValueUsed;
7123  if (CLI.RetSExt)
7124  MyFlags.Flags.setSExt();
7125  if (CLI.RetZExt)
7126  MyFlags.Flags.setZExt();
7127  if (CLI.IsInReg)
7128  MyFlags.Flags.setInReg();
7129  CLI.Ins.push_back(MyFlags);
7130  }
7131  }
7132  }
7133 
7134  // Handle all of the outgoing arguments.
7135  CLI.Outs.clear();
7136  CLI.OutVals.clear();
7137  ArgListTy &Args = CLI.getArgs();
7138  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7139  SmallVector<EVT, 4> ValueVTs;
7140  ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7141  Type *FinalType = Args[i].Ty;
7142  if (Args[i].isByVal)
7143  FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7144  bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7145  FinalType, CLI.CallConv, CLI.IsVarArg);
7146  for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7147  ++Value) {
7148  EVT VT = ValueVTs[Value];
7149  Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7150  SDValue Op = SDValue(Args[i].Node.getNode(),
7151  Args[i].Node.getResNo() + Value);
7153  unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7154 
7155  if (Args[i].isZExt)
7156  Flags.setZExt();
7157  if (Args[i].isSExt)
7158  Flags.setSExt();
7159  if (Args[i].isInReg)
7160  Flags.setInReg();
7161  if (Args[i].isSRet)
7162  Flags.setSRet();
7163  if (Args[i].isByVal)
7164  Flags.setByVal();
7165  if (Args[i].isInAlloca) {
7166  Flags.setInAlloca();
7167  // Set the byval flag for CCAssignFn callbacks that don't know about
7168  // inalloca. This way we can know how many bytes we should've allocated
7169  // and how many bytes a callee cleanup function will pop. If we port
7170  // inalloca to more targets, we'll have to add custom inalloca handling
7171  // in the various CC lowering callbacks.
7172  Flags.setByVal();
7173  }
7174  if (Args[i].isByVal || Args[i].isInAlloca) {
7175  PointerType *Ty = cast<PointerType>(Args[i].Ty);
7176  Type *ElementTy = Ty->getElementType();
7177  Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7178  // For ByVal, alignment should come from FE. BE will guess if this
7179  // info is not there but there are cases it cannot get right.
7180  unsigned FrameAlign;
7181  if (Args[i].Alignment)
7182  FrameAlign = Args[i].Alignment;
7183  else
7184  FrameAlign = getByValTypeAlignment(ElementTy);
7185  Flags.setByValAlign(FrameAlign);
7186  }
7187  if (Args[i].isNest)
7188  Flags.setNest();
7189  if (NeedsRegBlock)
7190  Flags.setInConsecutiveRegs();
7191  Flags.setOrigAlign(OriginalAlignment);
7192 
7193  MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7194  unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7195  SmallVector<SDValue, 4> Parts(NumParts);
7196  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7197 
7198  if (Args[i].isSExt)
7199  ExtendKind = ISD::SIGN_EXTEND;
7200  else if (Args[i].isZExt)
7201  ExtendKind = ISD::ZERO_EXTEND;
7202 
7203  // Conservatively only handle 'returned' on non-vectors for now
7204  if (Args[i].isReturned && !Op.getValueType().isVector()) {
7205  assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7206  "unexpected use of 'returned'");
7207  // Before passing 'returned' to the target lowering code, ensure that
7208  // either the register MVT and the actual EVT are the same size or that
7209  // the return value and argument are extended in the same way; in these
7210  // cases it's safe to pass the argument register value unchanged as the
7211  // return register value (although it's at the target's option whether
7212  // to do so)
7213  // TODO: allow code generation to take advantage of partially preserved
7214  // registers rather than clobbering the entire register when the
7215  // parameter extension method is not compatible with the return
7216  // extension method
7217  if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7218  (ExtendKind != ISD::ANY_EXTEND &&
7219  CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7220  Flags.setReturned();
7221  }
7222 
7223  getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7224  CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7225 
7226  for (unsigned j = 0; j != NumParts; ++j) {
7227  // if it isn't first piece, alignment must be 1
7228  ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7229  i < CLI.NumFixedArgs,
7230  i, j*Parts[j].getValueType().getStoreSize());
7231  if (NumParts > 1 && j == 0)
7232  MyFlags.Flags.setSplit();
7233  else if (j != 0)
7234  MyFlags.Flags.setOrigAlign(1);
7235 
7236  // Only mark the end at the last register of the last value.
7237  if (NeedsRegBlock && Value == NumValues - 1 && j == NumParts - 1)
7238  MyFlags.Flags.setInConsecutiveRegsLast();
7239 
7240  CLI.Outs.push_back(MyFlags);
7241  CLI.OutVals.push_back(Parts[j]);
7242  }
7243  }
7244  }
7245 
7246  SmallVector<SDValue, 4> InVals;
7247  CLI.Chain = LowerCall(CLI, InVals);
7248 
7249  // Verify that the target's LowerCall behaved as expected.
7250  assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7251  "LowerCall didn't return a valid chain!");
7252  assert((!CLI.IsTailCall || InVals.empty()) &&
7253  "LowerCall emitted a return value for a tail call!");
7254  assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7255  "LowerCall didn't emit the correct number of values!");
7256 
7257  // For a tail call, the return value is merely live-out and there aren't
7258  // any nodes in the DAG representing it. Return a special value to
7259  // indicate that a tail call has been emitted and no more Instructions
7260  // should be processed in the current block.
7261  if (CLI.IsTailCall) {
7262  CLI.DAG.setRoot(CLI.Chain);
7263  return std::make_pair(SDValue(), SDValue());
7264  }
7265 
7266  DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7267  assert(InVals[i].getNode() &&
7268  "LowerCall emitted a null value!");
7269  assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7270  "LowerCall emitted a value with the wrong type!");
7271  });
7272 
7273  SmallVector<SDValue, 4> ReturnValues;
7274  if (!CanLowerReturn) {
7275  // The instruction result is the result of loading from the
7276  // hidden sret parameter.
7277  SmallVector<EVT, 1> PVTs;
7278  Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7279 
7280  ComputeValueVTs(*this, PtrRetTy, PVTs);
7281  assert(PVTs.size() == 1 && "Pointers should fit in one register");
7282  EVT PtrVT = PVTs[0];
7283 
7284  unsigned NumValues = RetTys.size();
7285  ReturnValues.resize(NumValues);
7286  SmallVector<SDValue, 4> Chains(NumValues);
7287 
7288  for (unsigned i = 0; i < NumValues; ++i) {
7289  SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7290  CLI.DAG.getConstant(Offsets[i], PtrVT));
7291  SDValue L = CLI.DAG.getLoad(
7292  RetTys[i], CLI.DL, CLI.Chain, Add,
7293  MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7294  false, false, 1);
7295  ReturnValues[i] = L;
7296  Chains[i] = L.getValue(1);
7297  }
7298 
7299  CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7300  } else {
7301  // Collect the legal value parts into potentially illegal values
7302  // that correspond to the original function's return values.
7303  ISD::NodeType AssertOp = ISD::DELETED_NODE;
7304  if (CLI.RetSExt)
7305  AssertOp = ISD::AssertSext;
7306  else if (CLI.RetZExt)
7307  AssertOp = ISD::AssertZext;
7308  unsigned CurReg = 0;
7309  for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7310  EVT VT = RetTys[I];
7311  MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7312  unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7313 
7314  ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7315  NumRegs, RegisterVT, VT, nullptr,
7316  AssertOp));
7317  CurReg += NumRegs;
7318  }
7319 
7320  // For a function returning void, there is no return value. We can't create
7321  // such a node, so we just return a null return value in that case. In
7322  // that case, nothing will actually look at the value.
7323  if (ReturnValues.empty())
7324  return std::make_pair(SDValue(), CLI.Chain);
7325  }
7326 
7327  SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7328  CLI.DAG.getVTList(RetTys), ReturnValues);
7329  return std::make_pair(Res, CLI.Chain);
7330 }
void push_back(const T &Elt)
Definition: SmallVector.h:225
SDValue getValue(unsigned R) const
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
unsigned getPrefTypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:693
Type * getTypeForEVT(LLVMContext &Context) const
Definition: ValueTypes.cpp:180
unsigned getSizeInBits() const
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
const SDValue & setRoot(SDValue N)
Definition: SelectionDAG.h:333
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
MyFlags
Definition: YAMLIOTest.cpp:502
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
SDVTList getVTList(EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
SmallVector< ISD::InputArg, 32 > Ins
static int Value(bit_value_t V)
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
Definition: Type.h:125
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
const DomTreeNodeT * Node
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SmallVector< ISD::OutputArg, 32 > Outs
virtual SDValue LowerCall(CallLoweringInfo &, SmallVectorImpl< SDValue > &) const
void setOrigAlign(unsigned A)
Type * getElementType() const
Definition: DerivedTypes.h:319
SDNode * getNode() const
get the SDNode which holds the desired result
void GetReturnInfo(Type *ReturnType, AttributeSet attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI)
assert(Globals.size() > 1)
static Type * getVoidTy(LLVMContext &C)
Definition: Type.cpp:221
const DataLayout * getDataLayout() const
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
virtual unsigned getByValTypeAlignment(Type *Ty) const
#define DEBUG(X)
std::vector< ArgListEntry > ArgListTy
unsigned getABITypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:683
static PointerType * getUnqual(Type *ElementType)
Definition: DerivedTypes.h:456
const char * Args[]
uint64_t getTypeAllocSize(Type *Ty) const
Definition: DataLayout.h:368
MachineFrameInfo * getFrameInfo()
static void getCopyToParts(SelectionDAG &DAG, SDLoc DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, ISD::NodeType ExtendKind=ISD::ANY_EXTEND)
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, ISD::NodeType AssertOp=ISD::DELETED_NODE)
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI)
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
SmallVector< SDValue, 32 > OutVals
void ComputeValueVTs(const TargetLowering &TLI, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
#define I(x, y, z)
Definition: MD5.cpp:54
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
LLVM Value Representation.
Definition: Value.h:69
SDValue llvm::AArch64TargetLowering::LowerCONCAT_VECTORS ( SDValue  Op,
SelectionDAG DAG 
) const
private
SDValue AArch64TargetLowering::LowerConstantPool ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3440 of file AArch64ISelLowering.cpp.

3441  {
3442  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3443  EVT PtrVT = getPointerTy();
3444  SDLoc DL(Op);
3445 
3446  if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3447  // Use the GOT for the large code model on iOS.
3448  if (Subtarget->isTargetMachO()) {
3449  SDValue GotAddr = DAG.getTargetConstantPool(
3450  CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3452  return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3453  }
3454 
3455  const unsigned char MO_NC = AArch64II::MO_NC;
3456  return DAG.getNode(
3457  AArch64ISD::WrapperLarge, DL, PtrVT,
3458  DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3459  CP->getOffset(), AArch64II::MO_G3),
3460  DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3461  CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3462  DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3463  CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3464  DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3465  CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3466  } else {
3467  // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3468  // ELF, the only valid one on Darwin.
3469  SDValue Hi =
3470  DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3471  CP->getOffset(), AArch64II::MO_PAGE);
3473  CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3475 
3476  SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3477  return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3478  }
3479 }
const TargetMachine & getTargetMachine() const
const AArch64Subtarget * Subtarget
const DataLayout * DL
True if this is a little endian target.
virtual MVT getPointerTy(uint32_t=0) const
const Constant * getConstVal() const
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:450
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getAlignment() const
SDValue AArch64TargetLowering::LowerCTPOP ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3060 of file AArch64ISelLowering.cpp.

3060  {
3063  return SDValue();
3064 
3065  // While there is no integer popcount instruction, it can
3066  // be more efficiently lowered to the following sequence that uses
3067  // AdvSIMD registers/instructions as long as the copies to/from
3068  // the AdvSIMD registers are cheap.
3069  // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3070  // CNT V0.8B, V0.8B // 8xbyte pop-counts
3071  // ADDV B0, V0.8B // sum 8xbyte pop-counts
3072  // UMOV X0, V0.B[0] // copy byte result back to integer reg
3073  SDValue Val = Op.getOperand(0);
3074  SDLoc DL(Op);
3075  EVT VT = Op.getValueType();
3076  SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);
3077 
3078  SDValue VecVal;
3079  if (VT == MVT::i32) {
3080  VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
3081  VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec,
3082  VecVal);
3083  } else {
3084  VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3085  }
3086 
3087  SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
3088  SDValue UaddLV = DAG.getNode(
3090  DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3091 
3092  if (VT == MVT::i64)
3093  UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3094  return UaddLV;
3095 }
const Function * getFunction() const
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:872
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
const DataLayout * DL
True if this is a little endian target.
SDValue getUNDEF(EVT VT)
getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:625
const SDValue & getOperand(unsigned i) const
SDValue getTargetInsertSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand, SDValue Subreg)
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:170
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Disable implicit floating point insts.
Definition: Attributes.h:86
virtual const MCExpr* llvm::TargetLowering::LowerCustomJumpTableEntry ( const MachineJumpTableInfo ,
const MachineBasicBlock ,
unsigned  ,
MCContext  
) const
inlinevirtualinherited

Reimplemented in llvm::X86TargetLowering.

Definition at line 1894 of file TargetLowering.h.

1896  {
1897  llvm_unreachable("Need to implement this hook if target has custom JTIs");
1898  }
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
SDValue AArch64TargetLowering::LowerDarwin_VASTART ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3504 of file AArch64ISelLowering.cpp.

3505  {
3506  AArch64FunctionInfo *FuncInfo =
3508 
3509  SDLoc DL(Op);
3510  SDValue FR =
3511  DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3512  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3513  return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3514  MachinePointerInfo(SV), false, false, 0);
3515 }
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
const DataLayout * DL
True if this is a little endian target.
virtual MVT getPointerTy(uint32_t=0) const
const SDValue & getOperand(unsigned i) const
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
LLVM Value Representation.
Definition: Value.h:69
SDValue AArch64TargetLowering::LowerDarwinGlobalTLSAddress ( SDValue  Op,
SelectionDAG DAG 
) const
private

Convert a TLS address reference into the correct sequence of loads and calls to compute the variable's address (for Darwin, currently) and return an SDValue containing the final node.

Darwin only has one TLS scheme which must be capable of dealing with the fully general situation, in the worst case. This means:

  • "extern __thread" declaration.
  • Defined in a possibly unknown dynamic library.

The general system is that each __thread variable has a [3 x i64] descriptor which contains information used by the runtime to calculate the address. The only part of this the compiler needs to know about is the first xword, which contains a function pointer that must be called with the address of the entire descriptor in "x0".

Since this descriptor may be in a different unit, in general even the descriptor must be accessed via an indirect load. The "ideal" code sequence is: adrp x0, _var ldr x0, [x0, _var] ; x0 now contains address of descriptor ldr x1, [x0] ; x1 contains 1st entry of descriptor, ; the function pointer blr x1 ; Uses descriptor address in x0 ; Address of _var is now in x0.

If the address of _var's descriptor is known to the linker, then it can change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for a slight efficiency gain.

Definition at line 2628 of file AArch64ISelLowering.cpp.

2629  {
2630  assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
2631 
2632  SDLoc DL(Op);
2633  MVT PtrVT = getPointerTy();
2634  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2635 
2636  SDValue TLVPAddr =
2637  DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2638  SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
2639 
2640  // The first entry in the descriptor is a function pointer that we must call
2641  // to obtain the address of the variable.
2642  SDValue Chain = DAG.getEntryNode();
2643  SDValue FuncTLVGet =
2644  DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
2645  false, true, true, 8);
2646  Chain = FuncTLVGet.getValue(1);
2647 
2649  MFI->setAdjustsStack(true);
2650 
2651  // TLS calls preserve all registers except those that absolutely must be
2652  // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2653  // silly).
2655  const AArch64RegisterInfo *ARI =
2656  static_cast<const AArch64RegisterInfo *>(TRI);
2657  const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2658 
2659  // Finally, we can make the call. This is just a degenerate version of a
2660  // normal AArch64 call node: x0 takes the address of the descriptor, and
2661  // returns the address of the variable in this thread.
2662  Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
2663  Chain =
2665  Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
2666  DAG.getRegisterMask(Mask), Chain.getValue(1));
2667  return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
2668 }
SDValue getValue(unsigned R) const
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
const TargetMachine & getTargetMachine() const
const AArch64Subtarget * Subtarget
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:433
Abstract Stack Frame Information.
const DataLayout * DL
True if this is a little endian target.
SDVTList getVTList(EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
SDValue getRegisterMask(const uint32_t *RegMask)
assert(Globals.size() > 1)
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
const uint32_t * getTLSCallPreservedMask() const
MachineFrameInfo * getFrameInfo()
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
bool isTargetDarwin() const
static MachinePointerInfo getGOT()
virtual const TargetRegisterInfo * getRegisterInfo() const
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue AArch64TargetLowering::LowerELFGlobalTLSAddress ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 2732 of file AArch64ISelLowering.cpp.

2733  {
2734  assert(Subtarget->isTargetELF() && "This function expects an ELF target");
2735  assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2736  "ELF TLS only supported in small memory model");
2737  const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2738 
2740 
2741  SDValue TPOff;
2742  EVT PtrVT = getPointerTy();
2743  SDLoc DL(Op);
2744  const GlobalValue *GV = GA->getGlobal();
2745 
2746  SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
2747 
2748  if (Model == TLSModel::LocalExec) {
2749  SDValue HiVar = DAG.getTargetGlobalAddress(
2750  GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2751  SDValue LoVar = DAG.getTargetGlobalAddress(
2752  GV, DL, PtrVT, 0,
2754 
2755  TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2756  DAG.getTargetConstant(16, MVT::i32)),
2757  0);
2758  TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar,
2759  DAG.getTargetConstant(0, MVT::i32)),
2760  0);
2761  } else if (Model == TLSModel::InitialExec) {
2762  TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2763  TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
2764  } else if (Model == TLSModel::LocalDynamic) {
2765  // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2766  // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2767  // the beginning of the module's TLS region, followed by a DTPREL offset
2768  // calculation.
2769 
2770  // These accesses will need deduplicating if there's more than one.
2771  AArch64FunctionInfo *MFI =
2774 
2775  // Accesses used in this sequence go via the TLS descriptor which lives in
2776  // the GOT. Prepare an address we can use to handle this.
2777  SDValue HiDesc = DAG.getTargetExternalSymbol(
2778  "_TLS_MODULE_BASE_", PtrVT, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2779  SDValue LoDesc = DAG.getTargetExternalSymbol(
2780  "_TLS_MODULE_BASE_", PtrVT,
2782 
2783  // First argument to the descriptor call is the address of the descriptor
2784  // itself.
2785  SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2786  DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2787 
2788  // The call needs a relocation too for linker relaxation. It doesn't make
2789  // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2790  // the address.
2791  SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2793 
2794  // Now we can calculate the offset from TPIDR_EL0 to this module's
2795  // thread-local area.
2796  TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2797 
2798  // Now use :dtprel_whatever: operations to calculate this variable's offset
2799  // in its thread-storage area.
2800  SDValue HiVar = DAG.getTargetGlobalAddress(
2802  SDValue LoVar = DAG.getTargetGlobalAddress(
2803  GV, DL, MVT::i64, 0,
2805 
2806  SDValue DTPOff =
2807  SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2808  DAG.getTargetConstant(16, MVT::i32)),
2809  0);
2810  DTPOff =
2811  SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, DTPOff, LoVar,
2812  DAG.getTargetConstant(0, MVT::i32)),
2813  0);
2814 
2815  TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff);
2816  } else if (Model == TLSModel::GeneralDynamic) {
2817  // Accesses used in this sequence go via the TLS descriptor which lives in
2818  // the GOT. Prepare an address we can use to handle this.
2819  SDValue HiDesc = DAG.getTargetGlobalAddress(
2820  GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2821  SDValue LoDesc = DAG.getTargetGlobalAddress(
2822  GV, DL, PtrVT, 0,
2824 
2825  // First argument to the descriptor call is the address of the descriptor
2826  // itself.
2827  SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2828  DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2829 
2830  // The call needs a relocation too for linker relaxation. It doesn't make
2831  // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2832  // the address.
2833  SDValue SymAddr =
2834  DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2835 
2836  // Finally we can make a call to calculate the offset from tpidr_el0.
2837  TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2838  } else
2839  llvm_unreachable("Unsupported ELF TLS access model");
2840 
2841  return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2842 }
const TargetMachine & getTargetMachine() const
const GlobalValue * getGlobal() const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
const AArch64Subtarget * Subtarget
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:433
const DataLayout * DL
True if this is a little endian target.
virtual MVT getPointerTy(uint32_t=0) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
assert(Globals.size() > 1)
SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:406
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue LowerELFTLSDescCall(SDValue SymAddr, SDValue DescAddr, SDLoc DL, SelectionDAG &DAG) const
MachineSDNode * getMachineNode(unsigned Opcode, SDLoc dl, EVT VT)
TLSModel::Model getTLSModel(const GlobalValue *GV) const
SDValue AArch64TargetLowering::LowerELFTLSDescCall ( SDValue  SymAddr,
SDValue  DescAddr,
SDLoc  DL,
SelectionDAG DAG 
) const
private

When accessing thread-local variables under either the general-dynamic or local-dynamic system, we make a "TLS-descriptor" call. The variable will have a descriptor, accessible via a PC-relative ADRP, and whose first entry is a function pointer to carry out the resolution. This function takes the address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All other registers (except LR, NZCV) are preserved.

Thus, the ideal call sequence on AArch64 is:

adrp x0, :tlsdesc:thread_var
ldr x8, [x0, :tlsdesc_lo12:thread_var]
add x0, x0, :tlsdesc_lo12:thread_var
.tlsdesccall thread_var
blr x8
(TPIDR_EL0 offset now in x0).

The ".tlsdesccall" directive instructs the assembler to insert a particular relocation to help the linker relax this sequence if it turns out to be too conservative.

FIXME: we currently produce an extra, duplicated, ADRP instruction, but this is harmless.

Definition at line 2692 of file AArch64ISelLowering.cpp.

2694  {
2695  EVT PtrVT = getPointerTy();
2696 
2697  // The function we need to call is simply the first entry in the GOT for this
2698  // descriptor, load it in preparation.
2699  SDValue Func = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, SymAddr);
2700 
2701  // TLS calls preserve all registers except those that absolutely must be
2702  // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2703  // silly).
2705  const AArch64RegisterInfo *ARI =
2706  static_cast<const AArch64RegisterInfo *>(TRI);
2707  const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2708 
2709  // The function takes only one argument: the address of the descriptor itself
2710  // in X0.
2711  SDValue Glue, Chain;
2712  Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
2713  Glue = Chain.getValue(1);
2714 
2715  // We're now ready to populate the argument list, as with a normal call:
2717  Ops.push_back(Chain);
2718  Ops.push_back(Func);
2719  Ops.push_back(SymAddr);
2720  Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
2721  Ops.push_back(DAG.getRegisterMask(Mask));
2722  Ops.push_back(Glue);
2723 
2724  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2725  Chain = DAG.getNode(AArch64ISD::TLSDESC_CALL, DL, NodeTys, Ops);
2726  Glue = Chain.getValue(1);
2727 
2728  return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
2729 }
SDValue getValue(unsigned R) const
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
const TargetMachine & getTargetMachine() const
const DataLayout * DL
True if this is a little endian target.
SDVTList getVTList(EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
SDValue getRegisterMask(const uint32_t *RegMask)
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
const uint32_t * getTLSCallPreservedMask() const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
virtual const TargetRegisterInfo * getRegisterInfo() const
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5674 of file AArch64ISelLowering.cpp.

5675  {
5676  EVT VT = Op.getOperand(0).getValueType();
5677  SDLoc dl(Op);
5678  // Just in case...
5679  if (!VT.isVector())
5680  return SDValue();
5681 
5683  if (!Cst)
5684  return SDValue();
5685  unsigned Val = Cst->getZExtValue();
5686 
5687  unsigned Size = Op.getValueType().getSizeInBits();
5688  if (Val == 0) {
5689  switch (Size) {
5690  case 8:
5691  return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
5692  Op.getOperand(0));
5693  case 16:
5694  return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
5695  Op.getOperand(0));
5696  case 32:
5697  return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
5698  Op.getOperand(0));
5699  case 64:
5700  return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
5701  Op.getOperand(0));
5702  default:
5703  llvm_unreachable("Unexpected vector type in extract_subvector!");
5704  }
5705  }
5706  // If this is extracting the upper 64-bits of a 128-bit vector, we match
5707  // that directly.
5708  if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
5709  return Op;
5710 
5711  return SDValue();
5712 }
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
EVT getVectorElementType() const
Definition: ValueTypes.h:217
const SDValue & getOperand(unsigned i) const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
SDValue getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand)
uint64_t getZExtValue() const
SDValue AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5639 of file AArch64ISelLowering.cpp.

5640  {
5641  assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
5642 
5643  // Check for non-constant or out of range lane.
5644  EVT VT = Op.getOperand(0).getValueType();
5646  if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
5647  return SDValue();
5648 
5649 
5650  // Insertion/extraction are legal for V128 types.
5651  if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5652  VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5653  return Op;
5654 
5655  if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5656  VT != MVT::v1i64 && VT != MVT::v2f32)
5657  return SDValue();
5658 
5659  // For V64 types, we perform extraction by expanding the value
5660  // to a V128 type and perform the extraction on that.
5661  SDLoc DL(Op);
5662  SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5663  EVT WideTy = WideVec.getValueType();
5664 
5665  EVT ExtrTy = WideTy.getVectorElementType();
5666  if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
5667  ExtrTy = MVT::i32;
5668 
5669  // For extractions, we just return the result directly.
5670  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
5671  Op.getOperand(1));
5672 }
const DataLayout * DL
True if this is a little endian target.
EVT getVectorElementType() const
Definition: ValueTypes.h:217
static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG)
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
uint64_t getZExtValue() const
SDValue AArch64TargetLowering::LowerF128Call ( SDValue  Op,
SelectionDAG DAG,
RTLIB::Libcall  Call 
) const
private

Definition at line 1197 of file AArch64ISelLowering.cpp.

1198  {
1200  for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1201  Ops.push_back(Op.getOperand(i));
1202 
1203  return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1204  SDLoc(Op)).first;
1205 }
unsigned getNumOperands() const
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
const SDValue & getOperand(unsigned i) const
SDValue AArch64TargetLowering::LowerFCOPYSIGN ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 2977 of file AArch64ISelLowering.cpp.

2978  {
2979  EVT VT = Op.getValueType();
2980  SDLoc DL(Op);
2981 
2982  SDValue In1 = Op.getOperand(0);
2983  SDValue In2 = Op.getOperand(1);
2984  EVT SrcVT = In2.getValueType();
2985  if (SrcVT != VT) {
2986  if (SrcVT == MVT::f32 && VT == MVT::f64)
2987  In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
2988  else if (SrcVT == MVT::f64 && VT == MVT::f32)
2989  In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
2990  else
2991  // FIXME: Src type is different, bail out for now. Can VT really be a
2992  // vector type?
2993  return SDValue();
2994  }
2995 
2996  EVT VecVT;
2997  EVT EltVT;
2998  SDValue EltMask, VecVal1, VecVal2;
2999  if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3000  EltVT = MVT::i32;
3001  VecVT = MVT::v4i32;
3002  EltMask = DAG.getConstant(0x80000000ULL, EltVT);
3003 
3004  if (!VT.isVector()) {
3005  VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3006  DAG.getUNDEF(VecVT), In1);
3007  VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3008  DAG.getUNDEF(VecVT), In2);
3009  } else {
3010  VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3011  VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3012  }
3013  } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3014  EltVT = MVT::i64;
3015  VecVT = MVT::v2i64;
3016 
3017  // We want to materialize a mask with the the high bit set, but the AdvSIMD
3018  // immediate moves cannot materialize that in a single instruction for
3019  // 64-bit elements. Instead, materialize zero and then negate it.
3020  EltMask = DAG.getConstant(0, EltVT);
3021 
3022  if (!VT.isVector()) {
3023  VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3024  DAG.getUNDEF(VecVT), In1);
3025  VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3026  DAG.getUNDEF(VecVT), In2);
3027  } else {
3028  VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3029  VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3030  }
3031  } else {
3032  llvm_unreachable("Invalid type for copysign!");
3033  }
3034 
3035  std::vector<SDValue> BuildVectorOps;
3036  for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i)
3037  BuildVectorOps.push_back(EltMask);
3038 
3039  SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps);
3040 
3041  // If we couldn't materialize the mask above, then the mask vector will be
3042  // the zero vector, and we need to negate it here.
3043  if (VT == MVT::f64 || VT == MVT::v2f64) {
3044  BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3045  BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3046  BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3047  }
3048 
3049  SDValue Sel =
3050  DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3051 
3052  if (VT == MVT::f32)
3053  return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3054  else if (VT == MVT::f64)
3055  return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3056  else
3057  return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3058 }
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
const DataLayout * DL
True if this is a little endian target.
SDValue getUNDEF(EVT VT)
getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:625
const SDValue & getOperand(unsigned i) const
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
SDValue getTargetInsertSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand, SDValue Subreg)
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand)
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
SDValue AArch64TargetLowering::LowerFormalArguments ( SDValue  Chain,
CallingConv::ID  CallConv,
bool  isVarArg,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SDLoc  DL,
SelectionDAG DAG,
SmallVectorImpl< SDValue > &  InVals 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 1663 of file AArch64ISelLowering.cpp.

1666  {
1667  MachineFunction &MF = DAG.getMachineFunction();
1668  MachineFrameInfo *MFI = MF.getFrameInfo();
1669 
1670  // Assign locations to all of the incoming arguments.
1672  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1673  getTargetMachine(), ArgLocs, *DAG.getContext());
1674 
1675  // At this point, Ins[].VT may already be promoted to i32. To correctly
1676  // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
1677  // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
1678  // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
1679  // we use a special version of AnalyzeFormalArguments to pass in ValVT and
1680  // LocVT.
1681  unsigned NumArgs = Ins.size();
1682  Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
1683  unsigned CurArgIdx = 0;
1684  for (unsigned i = 0; i != NumArgs; ++i) {
1685  MVT ValVT = Ins[i].VT;
1686  std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx);
1687  CurArgIdx = Ins[i].OrigArgIndex;
1688 
1689  // Get type of the original argument.
1690  EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
1691  MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
1692  // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
1693  if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
1694  ValVT = MVT::i8;
1695  else if (ActualMVT == MVT::i16)
1696  ValVT = MVT::i16;
1697 
1698  CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
1699  bool Res =
1700  AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
1701  assert(!Res && "Call operand has unhandled type");
1702  (void)Res;
1703  }
1704  assert(ArgLocs.size() == Ins.size());
1705  SmallVector<SDValue, 16> ArgValues;
1706  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1707  CCValAssign &VA = ArgLocs[i];
1708 
1709  if (Ins[i].Flags.isByVal()) {
1710  // Byval is used for HFAs in the PCS, but the system should work in a
1711  // non-compliant manner for larger structs.
1712  EVT PtrTy = getPointerTy();
1713  int Size = Ins[i].Flags.getByValSize();
1714  unsigned NumRegs = (Size + 7) / 8;
1715 
1716  // FIXME: This works on big-endian for composite byvals, which are the common
1717  // case. It should also work for fundamental types too.
1718  unsigned FrameIdx =
1719  MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
1720  SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
1721  InVals.push_back(FrameIdxN);
1722 
1723  continue;
1724  }
1725 
1726  if (VA.isRegLoc()) {
1727  // Arguments stored in registers.
1728  EVT RegVT = VA.getLocVT();
1729 
1730  SDValue ArgValue;
1731  const TargetRegisterClass *RC;
1732 
1733  if (RegVT == MVT::i32)
1734  RC = &AArch64::GPR32RegClass;
1735  else if (RegVT == MVT::i64)
1736  RC = &AArch64::GPR64RegClass;
1737  else if (RegVT == MVT::f16)
1738  RC = &AArch64::FPR16RegClass;
1739  else if (RegVT == MVT::f32)
1740  RC = &AArch64::FPR32RegClass;
1741  else if (RegVT == MVT::f64 || RegVT.is64BitVector())
1742  RC = &AArch64::FPR64RegClass;
1743  else if (RegVT == MVT::f128 || RegVT.is128BitVector())
1744  RC = &AArch64::FPR128RegClass;
1745  else
1746  llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1747 
1748  // Transform the arguments in physical registers into virtual ones.
1749  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1750  ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
1751 
1752  // If this is an 8, 16 or 32-bit value, it is really passed promoted
1753  // to 64 bits. Insert an assert[sz]ext to capture this, then
1754  // truncate to the right size.
1755  switch (VA.getLocInfo()) {
1756  default:
1757  llvm_unreachable("Unknown loc info!");
1758  case CCValAssign::Full:
1759  break;
1760  case CCValAssign::BCvt:
1761  ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
1762  break;
1763  case CCValAssign::AExt:
1764  case CCValAssign::SExt:
1765  case CCValAssign::ZExt:
1766  // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
1767  // nodes after our lowering.
1768  assert(RegVT == Ins[i].VT && "incorrect register location selected");
1769  break;
1770  }
1771 
1772  InVals.push_back(ArgValue);
1773 
1774  } else { // VA.isRegLoc()
1775  assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
1776  unsigned ArgOffset = VA.getLocMemOffset();
1777  unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1778 
1779  uint32_t BEAlign = 0;
1780  if (ArgSize < 8 && !Subtarget->isLittleEndian())
1781  BEAlign = 8 - ArgSize;
1782 
1783  int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
1784 
1785  // Create load nodes to retrieve arguments from the stack.
1786  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1787  SDValue ArgValue;
1788 
1789  // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1791  MVT MemVT = VA.getValVT();
1792 
1793  switch (VA.getLocInfo()) {
1794  default:
1795  break;
1796  case CCValAssign::BCvt:
1797  MemVT = VA.getLocVT();
1798  break;
1799  case CCValAssign::SExt:
1800  ExtType = ISD::SEXTLOAD;
1801  break;
1802  case CCValAssign::ZExt:
1803  ExtType = ISD::ZEXTLOAD;
1804  break;
1805  case CCValAssign::AExt:
1806  ExtType = ISD::EXTLOAD;
1807  break;
1808  }
1809 
1810  ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
1812  MemVT, false, false, false, nullptr);
1813 
1814  InVals.push_back(ArgValue);
1815  }
1816  }
1817 
1818  // varargs
1819  if (isVarArg) {
1820  if (!Subtarget->isTargetDarwin()) {
1821  // The AAPCS variadic function ABI is identical to the non-variadic
1822  // one. As a result there may be more arguments in registers and we should
1823  // save them for future reference.
1824  saveVarArgRegisters(CCInfo, DAG, DL, Chain);
1825  }
1826 
1828  // This will point to the next argument passed via stack.
1829  unsigned StackOffset = CCInfo.getNextStackOffset();
1830  // We currently pass all varargs at 8-byte alignment.
1831  StackOffset = ((StackOffset + 7) & ~7);
1832  AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
1833  }
1834 
1836  unsigned StackArgSize = CCInfo.getNextStackOffset();
1837  bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1838  if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
1839  // This is a non-standard ABI so by fiat I say we're allowed to make full
1840  // use of the stack area to be popped, which must be aligned to 16 bytes in
1841  // any case:
1842  StackArgSize = RoundUpToAlignment(StackArgSize, 16);
1843 
1844  // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
1845  // a multiple of 16.
1846  FuncInfo->setArgumentStackToRestore(StackArgSize);
1847 
1848  // This realignment carries over to the available bytes below. Our own
1849  // callers will guarantee the space is free by giving an aligned value to
1850  // CALLSEQ_START.
1851  }
1852  // Even if we're not expected to free up the space, it's useful to know how
1853  // much is there while considering tail calls (because we can reuse it).
1854  FuncInfo->setBytesInStackArgArea(StackArgSize);
1855 
1856  return Chain;
1857 }
MVT getValVT() const
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
LocInfo getLocInfo() const
const TargetMachine & getTargetMachine() const
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
unsigned getSizeInBits() const
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
const Function * getFunction() const
bool isRegLoc() const
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
bool isLittleEndian() const
const AArch64Subtarget * Subtarget
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
static void advance(T &it, size_t Val)
Reg
All possible values of the reg field in the ModR/M byte.
Abstract Stack Frame Information.
virtual MVT getPointerTy(uint32_t=0) const
void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL, SDValue &Chain) const
unsigned getLocReg() const
void setArgumentStackToRestore(unsigned bytes)
assert(Globals.size() > 1)
MVT getLocVT() const
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
unsigned GuaranteedTailCallOpt
arg_iterator arg_begin()
Definition: Function.h:417
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCValAssign - Represent assignment of one arg/retval to a location.
MachineFrameInfo * getFrameInfo()
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
bool isMemLoc() const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align)
Definition: MathExtras.h:593
bool isTargetDarwin() const
const TargetMachine & getTarget() const
void setBytesInStackArgArea(unsigned bytes)
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
Definition: ValueTypes.h:136
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
bool isSimple() const
Definition: ValueTypes.h:95
unsigned getLocMemOffset() const
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable)
bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const
bool is64BitVector() const
is64BitVector - Return true if this is a 64-bit vector type.
Definition: ValueTypes.h:131
MVT getSimpleVT() const
Definition: ValueTypes.h:204
SDValue AArch64TargetLowering::LowerFP_EXTEND ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 1358 of file AArch64ISelLowering.cpp.

1359  {
1360  assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1361 
1362  RTLIB::Libcall LC;
1364 
1365  return LowerF128Call(Op, DAG, LC);
1366 }
SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG, RTLIB::Libcall Call) const
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
Libcall getFPEXT(EVT OpVT, EVT RetVT)
EVT getValueType() const
SDValue AArch64TargetLowering::LowerFP_ROUND ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 1368 of file AArch64ISelLowering.cpp.

1369  {
1370  if (Op.getOperand(0).getValueType() != MVT::f128) {
1371  // It's legal except when f128 is involved
1372  return Op;
1373  }
1374 
1375  RTLIB::Libcall LC;
1377 
1378  // FP_ROUND node has a second operand indicating whether it is known to be
1379  // precise. That doesn't take part in the LibCall so we can't directly use
1380  // LowerF128Call.
1381  SDValue SrcVal = Op.getOperand(0);
1382  return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1383  /*isSigned*/ false, SDLoc(Op)).first;
1384 }
Libcall getFPROUND(EVT OpVT, EVT RetVT)
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
const SDValue & getOperand(unsigned i) const
EVT getValueType() const
SDValue AArch64TargetLowering::LowerFP_TO_INT ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 1411 of file AArch64ISelLowering.cpp.

1412  {
1413  if (Op.getOperand(0).getValueType().isVector())
1414  return LowerVectorFP_TO_INT(Op, DAG);
1415 
1416  if (Op.getOperand(0).getValueType() != MVT::f128) {
1417  // It's legal except when f128 is involved
1418  return Op;
1419  }
1420 
1421  RTLIB::Libcall LC;
1422  if (Op.getOpcode() == ISD::FP_TO_SINT)
1424  else
1426 
1428  for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1429  Ops.push_back(Op.getOperand(i));
1430 
1431  return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1432  SDLoc(Op)).first;
1433 }
void push_back(const T &Elt)
Definition: SmallVector.h:225
unsigned getNumOperands() const
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG)
const SDValue & getOperand(unsigned i) const
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
unsigned getOpcode() const
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
EVT getValueType() const
SDValue AArch64TargetLowering::LowerFRAMEADDR ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3666 of file AArch64ISelLowering.cpp.

3667  {
3669  MFI->setFrameAddressIsTaken(true);
3670 
3671  EVT VT = Op.getValueType();
3672  SDLoc DL(Op);
3673  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3674  SDValue FrameAddr =
3675  DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
3676  while (Depth--)
3677  FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
3678  MachinePointerInfo(), false, false, false, 0);
3679  return FrameAddr;
3680 }
void setFrameAddressIsTaken(bool T)
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
Abstract Stack Frame Information.
const DataLayout * DL
True if this is a little endian target.
const SDValue & getOperand(unsigned i) const
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
MachineFrameInfo * getFrameInfo()
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
EVT getValueType() const
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue AArch64TargetLowering::LowerFSINCOS ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 1486 of file AArch64ISelLowering.cpp.

1487  {
1488  // For iOS, we want to call an alternative entry point: __sincos_stret,
1489  // which returns the values in two S / D registers.
1490  SDLoc dl(Op);
1491  SDValue Arg = Op.getOperand(0);
1492  EVT ArgVT = Arg.getValueType();
1493  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1494 
1495  ArgListTy Args;
1496  ArgListEntry Entry;
1497 
1498  Entry.Node = Arg;
1499  Entry.Ty = ArgTy;
1500  Entry.isSExt = false;
1501  Entry.isZExt = false;
1502  Args.push_back(Entry);
1503 
1504  const char *LibcallName =
1505  (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1506  SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1507 
1508  StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
1510  CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1511  .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1512 
1513  std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1514  return CallResult.first;
1515 }
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
Type * getTypeForEVT(LLVMContext &Context) const
Definition: ValueTypes.cpp:180
SDValue getExternalSymbol(const char *Sym, EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
const SDValue & getOperand(unsigned i) const
std::vector< ArgListEntry > ArgListTy
const char * Args[]
static StructType * get(LLVMContext &Context, ArrayRef< Type * > Elements, bool isPacked=false)
Definition: Type.cpp:399
EVT getValueType() const
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue AArch64TargetLowering::LowerGlobalAddress ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 2559 of file AArch64ISelLowering.cpp.

2560  {
2561  EVT PtrVT = getPointerTy();
2562  SDLoc DL(Op);
2563  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2564  unsigned char OpFlags =
2566 
2567  assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2568  "unexpected offset in global node");
2569 
2570  // This also catched the large code model case for Darwin.
2571  if ((OpFlags & AArch64II::MO_GOT) != 0) {
2572  SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2573  // FIXME: Once remat is capable of dealing with instructions with register
2574  // operands, expand this into two nodes instead of using a wrapper node.
2575  return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2576  }
2577 
2578  if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2579  const unsigned char MO_NC = AArch64II::MO_NC;
2580  return DAG.getNode(
2581  AArch64ISD::WrapperLarge, DL, PtrVT,
2582  DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2583  DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2584  DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2585  DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
2586  } else {
2587  // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2588  // the only correct model on Darwin.
2589  SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2590  OpFlags | AArch64II::MO_PAGE);
2591  unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2592  SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2593 
2594  SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2595  return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2596  }
2597 }
const TargetMachine & getTargetMachine() const
const AArch64Subtarget * Subtarget
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:433
const DataLayout * DL
True if this is a little endian target.
virtual MVT getPointerTy(uint32_t=0) const
assert(Globals.size() > 1)
unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
static std::error_code getOffset(const SymbolRef &Sym, uint64_t &Result)
Definition: RuntimeDyld.cpp:76
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue AArch64TargetLowering::LowerGlobalTLSAddress ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 2844 of file AArch64ISelLowering.cpp.

2845  {
2846  if (Subtarget->isTargetDarwin())
2847  return LowerDarwinGlobalTLSAddress(Op, DAG);
2848  else if (Subtarget->isTargetELF())
2849  return LowerELFGlobalTLSAddress(Op, DAG);
2850 
2851  llvm_unreachable("Unexpected platform trying to use TLS");
2852 }
SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Convert a TLS address reference into the correct sequence of loads and calls to compute the variable'...
SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
const AArch64Subtarget * Subtarget
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
bool isTargetDarwin() const
SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5606 of file AArch64ISelLowering.cpp.

5607  {
5608  assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
5609 
5610  // Check for non-constant or out of range lane.
5611  EVT VT = Op.getOperand(0).getValueType();
5613  if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
5614  return SDValue();
5615 
5616 
5617  // Insertion/extraction are legal for V128 types.
5618  if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5619  VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5620  return Op;
5621 
5622  if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5623  VT != MVT::v1i64 && VT != MVT::v2f32)
5624  return SDValue();
5625 
5626  // For V64 types, we perform insertion by expanding the value
5627  // to a V128 type and perform the insertion on that.
5628  SDLoc DL(Op);
5629  SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5630  EVT WideTy = WideVec.getValueType();
5631 
5632  SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
5633  Op.getOperand(1), Op.getOperand(2));
5634  // Re-narrow the resultant vector.
5635  return NarrowVector(Node, DAG);
5636 }
const DataLayout * DL
True if this is a little endian target.
const DomTreeNodeT * Node
static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG)
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG)
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
uint64_t getZExtValue() const
SDValue AArch64TargetLowering::LowerINT_TO_FP ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 1463 of file AArch64ISelLowering.cpp.

1464  {
1465  if (Op.getValueType().isVector())
1466  return LowerVectorINT_TO_FP(Op, DAG);
1467 
1468  // i128 conversions are libcalls.
1469  if (Op.getOperand(0).getValueType() == MVT::i128)
1470  return SDValue();
1471 
1472  // Other conversions are legal, unless it's to the completely software-based
1473  // fp128.
1474  if (Op.getValueType() != MVT::f128)
1475  return Op;
1476 
1477  RTLIB::Libcall LC;
1478  if (Op.getOpcode() == ISD::SINT_TO_FP)
1480  else
1482 
1483  return LowerF128Call(Op, DAG, LC);
1484 }
static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG)
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG, RTLIB::Libcall Call) const
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
EVT getValueType() const
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
SDValue AArch64TargetLowering::LowerJumpTable ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3412 of file AArch64ISelLowering.cpp.

3413  {
3414  // Jump table entries as PC relative offsets. No additional tweaking
3415  // is necessary here. Just get the address of the jump table.
3416  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3417  EVT PtrVT = getPointerTy();
3418  SDLoc DL(Op);
3419 
3420  if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3421  !Subtarget->isTargetMachO()) {
3422  const unsigned char MO_NC = AArch64II::MO_NC;
3423  return DAG.getNode(
3424  AArch64ISD::WrapperLarge, DL, PtrVT,
3425  DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3426  DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3427  DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3428  DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3429  AArch64II::MO_G0 | MO_NC));
3430  }
3431 
3432  SDValue Hi =
3433  DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3434  SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3436  SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3437  return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3438 }
const TargetMachine & getTargetMachine() const
const AArch64Subtarget * Subtarget
const DataLayout * DL
True if this is a little endian target.
virtual MVT getPointerTy(uint32_t=0) const
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:444
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue AArch64TargetLowering::LowerOperation ( SDValue  Op,
SelectionDAG DAG 
) const
overridevirtual

LowerOperation - Provide custom lowering hooks for some operations.

Reimplemented from llvm::TargetLowering.

Definition at line 1533 of file AArch64ISelLowering.cpp.

1534  {
1535  switch (Op.getOpcode()) {
1536  default:
1537  llvm_unreachable("unimplemented operand");
1538  return SDValue();
1539  case ISD::BITCAST:
1540  return LowerBITCAST(Op, DAG);
1541  case ISD::GlobalAddress:
1542  return LowerGlobalAddress(Op, DAG);
1543  case ISD::GlobalTLSAddress:
1544  return LowerGlobalTLSAddress(Op, DAG);
1545  case ISD::SETCC:
1546  return LowerSETCC(Op, DAG);
1547  case ISD::BR_CC:
1548  return LowerBR_CC(Op, DAG);
1549  case ISD::SELECT:
1550  return LowerSELECT(Op, DAG);
1551  case ISD::SELECT_CC:
1552  return LowerSELECT_CC(Op, DAG);
1553  case ISD::JumpTable:
1554  return LowerJumpTable(Op, DAG);
1555  case ISD::ConstantPool:
1556  return LowerConstantPool(Op, DAG);
1557  case ISD::BlockAddress:
1558  return LowerBlockAddress(Op, DAG);
1559  case ISD::VASTART:
1560  return LowerVASTART(Op, DAG);
1561  case ISD::VACOPY:
1562  return LowerVACOPY(Op, DAG);
1563  case ISD::VAARG:
1564  return LowerVAARG(Op, DAG);
1565  case ISD::ADDC:
1566  case ISD::ADDE:
1567  case ISD::SUBC:
1568  case ISD::SUBE:
1569  return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1570  case ISD::SADDO:
1571  case ISD::UADDO:
1572  case ISD::SSUBO:
1573  case ISD::USUBO:
1574  case ISD::SMULO:
1575  case ISD::UMULO:
1576  return LowerXALUO(Op, DAG);
1577  case ISD::FADD:
1578  return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1579  case ISD::FSUB:
1580  return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1581  case ISD::FMUL:
1582  return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1583  case ISD::FDIV:
1584  return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1585  case ISD::FP_ROUND:
1586  return LowerFP_ROUND(Op, DAG);
1587  case ISD::FP_EXTEND:
1588  return LowerFP_EXTEND(Op, DAG);
1589  case ISD::FRAMEADDR:
1590  return LowerFRAMEADDR(Op, DAG);
1591  case ISD::RETURNADDR:
1592  return LowerRETURNADDR(Op, DAG);
1594  return LowerINSERT_VECTOR_ELT(Op, DAG);
1596  return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1597  case ISD::BUILD_VECTOR:
1598  return LowerBUILD_VECTOR(Op, DAG);
1599  case ISD::VECTOR_SHUFFLE:
1600  return LowerVECTOR_SHUFFLE(Op, DAG);
1602  return LowerEXTRACT_SUBVECTOR(Op, DAG);
1603  case ISD::SRA:
1604  case ISD::SRL:
1605  case ISD::SHL:
1606  return LowerVectorSRA_SRL_SHL(Op, DAG);
1607  case ISD::SHL_PARTS:
1608  return LowerShiftLeftParts(Op, DAG);
1609  case ISD::SRL_PARTS:
1610  case ISD::SRA_PARTS:
1611  return LowerShiftRightParts(Op, DAG);
1612  case ISD::CTPOP:
1613  return LowerCTPOP(Op, DAG);
1614  case ISD::FCOPYSIGN:
1615  return LowerFCOPYSIGN(Op, DAG);
1616  case ISD::AND:
1617  return LowerVectorAND(Op, DAG);
1618  case ISD::OR:
1619  return LowerVectorOR(Op, DAG);
1620  case ISD::XOR:
1621  return LowerXOR(Op, DAG);
1622  case ISD::PREFETCH:
1623  return LowerPREFETCH(Op, DAG);
1624  case ISD::SINT_TO_FP:
1625  case ISD::UINT_TO_FP:
1626  return LowerINT_TO_FP(Op, DAG);
1627  case ISD::FP_TO_SINT:
1628  case ISD::FP_TO_UINT:
1629  return LowerFP_TO_INT(Op, DAG);
1630  case ISD::FSINCOS:
1631  return LowerFSINCOS(Op, DAG);
1632  }
1633 }
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const
static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG)
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const
static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG)
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const
Same for subtraction.
Definition: ISDOpcodes.h:221
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG, RTLIB::Libcall Call) const
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
Simple binary floating point operators.
Definition: ISDOpcodes.h:227
unsigned getOpcode() const
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG)
SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const
static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG)
SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const
Same for multiplication.
Definition: ISDOpcodes.h:224
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:490
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVectorAND(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const
void TargetLowering::LowerOperationWrapper ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG 
) const
virtualinherited

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types. It replaces the LowerOperation callback in the type Legalizer. The reason we can not do away with LowerOperation entirely is that LegalizeDAG isn't yet ready to use this callback.

TODO: Consider merging with ReplaceNodeResults.

The target places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all. The default implementation calls LowerOperation.

Reimplemented in llvm::MipsTargetLowering.

Definition at line 7332 of file SelectionDAGBuilder.cpp.

7334  {
7335  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7336  if (Res.getNode())
7337  Results.push_back(Res);
7338 }
SDNode * getNode() const
get the SDNode which holds the desired result
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const
SDValue AArch64TargetLowering::LowerReturn ( SDValue  Chain,
CallingConv::ID  CallConv,
bool  isVarArg,
const SmallVectorImpl< ISD::OutputArg > &  Outs,
const SmallVectorImpl< SDValue > &  OutVals,
SDLoc  DL,
SelectionDAG DAG 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 2502 of file AArch64ISelLowering.cpp.

2506  {
2508  ? RetCC_AArch64_WebKit_JS
2509  : RetCC_AArch64_AAPCS;
2511  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2512  getTargetMachine(), RVLocs, *DAG.getContext());
2513  CCInfo.AnalyzeReturn(Outs, RetCC);
2514 
2515  // Copy the result values into the output registers.
2516  SDValue Flag;
2517  SmallVector<SDValue, 4> RetOps(1, Chain);
2518  for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2519  ++i, ++realRVLocIdx) {
2520  CCValAssign &VA = RVLocs[i];
2521  assert(VA.isRegLoc() && "Can only return in registers!");
2522  SDValue Arg = OutVals[realRVLocIdx];
2523 
2524  switch (VA.getLocInfo()) {
2525  default:
2526  llvm_unreachable("Unknown loc info!");
2527  case CCValAssign::Full:
2528  if (Outs[i].ArgVT == MVT::i1) {
2529  // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2530  // value. This is strictly redundant on Darwin (which uses "zeroext
2531  // i1"), but will be optimised out before ISel.
2532  Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2533  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2534  }
2535  break;
2536  case CCValAssign::BCvt:
2537  Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2538  break;
2539  }
2540 
2541  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2542  Flag = Chain.getValue(1);
2543  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2544  }
2545 
2546  RetOps[0] = Chain; // Update chain.
2547 
2548  // Add the flag if we have it.
2549  if (Flag.getNode())
2550  RetOps.push_back(Flag);
2551 
2552  return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2553 }
SDValue getValue(unsigned R) const
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
LocInfo getLocInfo() const
const TargetMachine & getTargetMachine() const
bool isRegLoc() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
unsigned getLocReg() const
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
MVT getLocVT() const
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCValAssign - Represent assignment of one arg/retval to a location.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
SDValue getRegister(unsigned Reg, EVT VT)
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
SDValue AArch64TargetLowering::LowerRETURNADDR ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3694 of file AArch64ISelLowering.cpp.

3695  {
3696  MachineFunction &MF = DAG.getMachineFunction();
3697  MachineFrameInfo *MFI = MF.getFrameInfo();
3698  MFI->setReturnAddressIsTaken(true);
3699 
3700  EVT VT = Op.getValueType();
3701  SDLoc DL(Op);
3702  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3703  if (Depth) {
3704  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3705  SDValue Offset = DAG.getConstant(8, getPointerTy());
3706  return DAG.getLoad(VT, DL, DAG.getEntryNode(),
3707  DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
3708  MachinePointerInfo(), false, false, false, 0);
3709  }
3710 
3711  // Return LR, which contains the return address. Mark it an implicit live-in.
3712  unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
3713  return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
3714 }
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
Reg
All possible values of the reg field in the ModR/M byte.
Abstract Stack Frame Information.
const DataLayout * DL
True if this is a little endian target.
virtual MVT getPointerTy(uint32_t=0) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
const SDValue & getOperand(unsigned i) const
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
MachineFrameInfo * getFrameInfo()
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
void setReturnAddressIsTaken(bool s)
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue llvm::AArch64TargetLowering::LowerSCALAR_TO_VECTOR ( SDValue  Op,
SelectionDAG DAG 
) const
private
SDValue AArch64TargetLowering::LowerSELECT ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3194 of file AArch64ISelLowering.cpp.

3195  {
3196  SDValue CC = Op->getOperand(0);
3197  SDValue TVal = Op->getOperand(1);
3198  SDValue FVal = Op->getOperand(2);
3199  SDLoc DL(Op);
3200 
3201  unsigned Opc = CC.getOpcode();
3202  // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3203  // instruction.
3204  if (CC.getResNo() == 1 &&
3205  (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3206  Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3207  // Only lower legal XALUO ops.
3208  if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
3209  return SDValue();
3210 
3211  AArch64CC::CondCode OFCC;
3212  SDValue Value, Overflow;
3213  std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG);
3214  SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3215 
3216  return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3217  CCVal, Overflow);
3218  }
3219 
3220  if (CC.getOpcode() == ISD::SETCC)
3221  return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
3222  cast<CondCodeSDNode>(CC.getOperand(2))->get());
3223  else
3224  return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
3225  FVal, ISD::SETNE);
3226 }
SDValue getValue(unsigned R) const
SDValue getSelectCC(SDLoc DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Definition: SelectionDAG.h:716
const SDValue & getOperand(unsigned Num) const
Same for subtraction.
Definition: ISDOpcodes.h:221
static std::pair< SDValue, SDValue > getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG)
unsigned getResNo() const
get the index which selects a specific result in the SDNode
EVT getValueType(unsigned ResNo) const
const DataLayout * DL
True if this is a little endian target.
static int Value(bit_value_t V)
bool isTypeLegal(EVT VT) const
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Same for multiplication.
Definition: ISDOpcodes.h:224
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
SDValue AArch64TargetLowering::LowerSELECT_CC ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3228 of file AArch64ISelLowering.cpp.

3229  {
3230  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3231  SDValue LHS = Op.getOperand(0);
3232  SDValue RHS = Op.getOperand(1);
3233  SDValue TVal = Op.getOperand(2);
3234  SDValue FVal = Op.getOperand(3);
3235  SDLoc dl(Op);
3236 
3237  // Handle f128 first, because it will result in a comparison of some RTLIB
3238  // call result against zero.
3239  if (LHS.getValueType() == MVT::f128) {
3240  softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3241 
3242  // If softenSetCCOperands returned a scalar, we need to compare the result
3243  // against zero to select between true and false values.
3244  if (!RHS.getNode()) {
3245  RHS = DAG.getConstant(0, LHS.getValueType());
3246  CC = ISD::SETNE;
3247  }
3248  }
3249 
3250  // Handle integers first.
3251  if (LHS.getValueType().isInteger()) {
3252  assert((LHS.getValueType() == RHS.getValueType()) &&
3253  (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3254 
3255  unsigned Opcode = AArch64ISD::CSEL;
3256 
3257  // If both the TVal and the FVal are constants, see if we can swap them in
3258  // order to for a CSINV or CSINC out of them.
3259  ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3260  ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3261 
3262  if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3263  std::swap(TVal, FVal);
3264  std::swap(CTVal, CFVal);
3265  CC = ISD::getSetCCInverse(CC, true);
3266  } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3267  std::swap(TVal, FVal);
3268  std::swap(CTVal, CFVal);
3269  CC = ISD::getSetCCInverse(CC, true);
3270  } else if (TVal.getOpcode() == ISD::XOR) {
3271  // If TVal is a NOT we want to swap TVal and FVal so that we can match
3272  // with a CSINV rather than a CSEL.
3274 
3275  if (CVal && CVal->isAllOnesValue()) {
3276  std::swap(TVal, FVal);
3277  std::swap(CTVal, CFVal);
3278  CC = ISD::getSetCCInverse(CC, true);
3279  }
3280  } else if (TVal.getOpcode() == ISD::SUB) {
3281  // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3282  // that we can match with a CSNEG rather than a CSEL.
3284 
3285  if (CVal && CVal->isNullValue()) {
3286  std::swap(TVal, FVal);
3287  std::swap(CTVal, CFVal);
3288  CC = ISD::getSetCCInverse(CC, true);
3289  }
3290  } else if (CTVal && CFVal) {
3291  const int64_t TrueVal = CTVal->getSExtValue();
3292  const int64_t FalseVal = CFVal->getSExtValue();
3293  bool Swap = false;
3294 
3295  // If both TVal and FVal are constants, see if FVal is the
3296  // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3297  // instead of a CSEL in that case.
3298  if (TrueVal == ~FalseVal) {
3299  Opcode = AArch64ISD::CSINV;
3300  } else if (TrueVal == -FalseVal) {
3301  Opcode = AArch64ISD::CSNEG;
3302  } else if (TVal.getValueType() == MVT::i32) {
3303  // If our operands are only 32-bit wide, make sure we use 32-bit
3304  // arithmetic for the check whether we can use CSINC. This ensures that
3305  // the addition in the check will wrap around properly in case there is
3306  // an overflow (which would not be the case if we do the check with
3307  // 64-bit arithmetic).
3308  const uint32_t TrueVal32 = CTVal->getZExtValue();
3309  const uint32_t FalseVal32 = CFVal->getZExtValue();
3310 
3311  if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3312  Opcode = AArch64ISD::CSINC;
3313 
3314  if (TrueVal32 > FalseVal32) {
3315  Swap = true;
3316  }
3317  }
3318  // 64-bit check whether we can use CSINC.
3319  } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3320  Opcode = AArch64ISD::CSINC;
3321 
3322  if (TrueVal > FalseVal) {
3323  Swap = true;
3324  }
3325  }
3326 
3327  // Swap TVal and FVal if necessary.
3328  if (Swap) {
3329  std::swap(TVal, FVal);
3330  std::swap(CTVal, CFVal);
3331  CC = ISD::getSetCCInverse(CC, true);
3332  }
3333 
3334  if (Opcode != AArch64ISD::CSEL) {
3335  // Drop FVal since we can get its value by simply inverting/negating
3336  // TVal.
3337  FVal = TVal;
3338  }
3339  }
3340 
3341  SDValue CCVal;
3342  SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3343 
3344  EVT VT = Op.getValueType();
3345  return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3346  }
3347 
3348  // Now we know we're dealing with FP values.
3349  assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3350  assert(LHS.getValueType() == RHS.getValueType());
3351  EVT VT = Op.getValueType();
3352 
3353  // Try to match this select into a max/min operation, which have dedicated
3354  // opcode in the instruction set.
3355  // FIXME: This is not correct in the presence of NaNs, so we only enable this
3356  // in no-NaNs mode.
3357  if (getTargetMachine().Options.NoNaNsFPMath) {
3358  SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3359  if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3360  selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3362  std::swap(MinMaxLHS, MinMaxRHS);
3363  }
3364 
3365  if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3366  selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3367  switch (CC) {
3368  default:
3369  break;
3370  case ISD::SETGT:
3371  case ISD::SETGE:
3372  case ISD::SETUGT:
3373  case ISD::SETUGE:
3374  case ISD::SETOGT:
3375  case ISD::SETOGE:
3376  return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3377  break;
3378  case ISD::SETLT:
3379  case ISD::SETLE:
3380  case ISD::SETULT:
3381  case ISD::SETULE:
3382  case ISD::SETOLT:
3383  case ISD::SETOLE:
3384  return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3385  break;
3386  }
3387  }
3388  }
3389 
3390  // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3391  // and do the comparison.
3392  SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3393 
3394  // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3395  // clean. Some of them require two CSELs to implement.
3396  AArch64CC::CondCode CC1, CC2;
3397  changeFPCCToAArch64CC(CC, CC1, CC2);
3398  SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3399  SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3400 
3401  // If we need a second CSEL, emit it, using the output of the first as the
3402  // RHS. We're effectively OR'ing the two CC's together.
3403  if (CC2 != AArch64CC::AL) {
3404  SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3405  return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3406  }
3407 
3408  // Otherwise, return the output of the first CSEL.
3409  return CS1;
3410 }
const TargetMachine & getTargetMachine() const
bool isAllOnesValue() const
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl)
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
CondCode getSetCCSwappedOperands(CondCode Operation)
static void changeFPCCToAArch64CC(ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2)
changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
CondCode getSetCCInverse(CondCode Operation, bool isInteger)
static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result)
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:590
int64_t getSExtValue() const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl, SelectionDAG &DAG)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
std::string Options
Definition: llvm-ar.cpp:73
uint64_t getZExtValue() const
void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const
SDValue AArch64TargetLowering::LowerSETCC ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3097 of file AArch64ISelLowering.cpp.

3097  {
3098 
3099  if (Op.getValueType().isVector())
3100  return LowerVSETCC(Op, DAG);
3101 
3102  SDValue LHS = Op.getOperand(0);
3103  SDValue RHS = Op.getOperand(1);
3104  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3105  SDLoc dl(Op);
3106 
3107  // We chose ZeroOrOneBooleanContents, so use zero and one.
3108  EVT VT = Op.getValueType();
3109  SDValue TVal = DAG.getConstant(1, VT);
3110  SDValue FVal = DAG.getConstant(0, VT);
3111 
3112  // Handle f128 first, since one possible outcome is a normal integer
3113  // comparison which gets picked up by the next if statement.
3114  if (LHS.getValueType() == MVT::f128) {
3115  softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3116 
3117  // If softenSetCCOperands returned a scalar, use it.
3118  if (!RHS.getNode()) {
3119  assert(LHS.getValueType() == Op.getValueType() &&
3120  "Unexpected setcc expansion!");
3121  return LHS;
3122  }
3123  }
3124 
3125  if (LHS.getValueType().isInteger()) {
3126  SDValue CCVal;
3127  SDValue Cmp =
3128  getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3129 
3130  // Note that we inverted the condition above, so we reverse the order of
3131  // the true and false operands here. This will allow the setcc to be
3132  // matched to a single CSINC instruction.
3133  return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3134  }
3135 
3136  // Now we know we're dealing with FP values.
3137  assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3138 
3139  // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3140  // and do the comparison.
3141  SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3142 
3143  AArch64CC::CondCode CC1, CC2;
3144  changeFPCCToAArch64CC(CC, CC1, CC2);
3145  if (CC2 == AArch64CC::AL) {
3146  changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3147  SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3148 
3149  // Note that we inverted the condition above, so we reverse the order of
3150  // the true and false operands here. This will allow the setcc to be
3151  // matched to a single CSINC instruction.
3152  return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3153  } else {
3154  // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3155  // totally clean. Some of them require two CSELs to implement. As is in
3156  // this case, we emit the first CSEL and then emit a second using the output
3157  // of the first as the RHS. We're effectively OR'ing the two CC's together.
3158 
3159  // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3160  SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3161  SDValue CS1 =
3162  DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3163 
3164  SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3165  return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3166  }
3167 }
SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl)
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
static void changeFPCCToAArch64CC(ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2)
changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
CondCode getSetCCInverse(CondCode Operation, bool isInteger)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl, SelectionDAG &DAG)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const
SDValue AArch64TargetLowering::LowerShiftLeftParts ( SDValue  Op,
SelectionDAG DAG 
) const
private

LowerShiftLeftParts - Lower SHL_PARTS, which returns two i64 values and take a 2 x i64 value to shift plus a shift amount.

Definition at line 3764 of file AArch64ISelLowering.cpp.

3765  {
3766  assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3767  EVT VT = Op.getValueType();
3768  unsigned VTBits = VT.getSizeInBits();
3769  SDLoc dl(Op);
3770  SDValue ShOpLo = Op.getOperand(0);
3771  SDValue ShOpHi = Op.getOperand(1);
3772  SDValue ShAmt = Op.getOperand(2);
3773  SDValue ARMcc;
3774 
3775  assert(Op.getOpcode() == ISD::SHL_PARTS);
3776  SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3777  DAG.getConstant(VTBits, MVT::i64), ShAmt);
3778  SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3779  SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3780  DAG.getConstant(VTBits, MVT::i64));
3781  SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3782  SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3783 
3784  SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3785 
3786  SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3787  ISD::SETGE, dl, DAG);
3788  SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3789  SDValue Hi =
3790  DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
3791 
3792  // AArch64 shifts of larger than register sizes are wrapped rather than
3793  // clamped, so we can't just emit "lo << a" if a is too big.
3794  SDValue TrueValLo = DAG.getConstant(0, VT);
3795  SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3796  SDValue Lo =
3797  DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3798 
3799  SDValue Ops[2] = { Lo, Hi };
3800  return DAG.getMergeValues(Ops, dl);
3801 }
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
getMergeValues - Create a MERGE_VALUES node from the given operands.
unsigned getNumOperands() const
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl, SelectionDAG &DAG)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue AArch64TargetLowering::LowerShiftRightParts ( SDValue  Op,
SelectionDAG DAG 
) const
private

LowerShiftRightParts - Lower SRA_PARTS, which returns two i64 values and take a 2 x i64 value to shift plus a shift amount.

Definition at line 3718 of file AArch64ISelLowering.cpp.

3719  {
3720  assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3721  EVT VT = Op.getValueType();
3722  unsigned VTBits = VT.getSizeInBits();
3723  SDLoc dl(Op);
3724  SDValue ShOpLo = Op.getOperand(0);
3725  SDValue ShOpHi = Op.getOperand(1);
3726  SDValue ShAmt = Op.getOperand(2);
3727  SDValue ARMcc;
3728  unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3729 
3731 
3732  SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3733  DAG.getConstant(VTBits, MVT::i64), ShAmt);
3734  SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3735  SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3736  DAG.getConstant(VTBits, MVT::i64));
3737  SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3738 
3739  SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3740  ISD::SETGE, dl, DAG);
3741  SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3742 
3743  SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3744  SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3745  SDValue Lo =
3746  DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3747 
3748  // AArch64 shifts larger than the register width are wrapped rather than
3749  // clamped, so we can't just emit "hi >> x".
3750  SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3751  SDValue TrueValHi = Opc == ISD::SRA
3752  ? DAG.getNode(Opc, dl, VT, ShOpHi,
3753  DAG.getConstant(VTBits - 1, MVT::i64))
3754  : DAG.getConstant(0, VT);
3755  SDValue Hi =
3756  DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
3757 
3758  SDValue Ops[2] = { Lo, Hi };
3759  return DAG.getMergeValues(Ops, dl);
3760 }
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
getMergeValues - Create a MERGE_VALUES node from the given operands.
unsigned getNumOperands() const
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl, SelectionDAG &DAG)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue AArch64TargetLowering::LowerVAARG ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3604 of file AArch64ISelLowering.cpp.

3604  {
3606  "automatic va_arg instruction only works on Darwin");
3607 
3608  const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3609  EVT VT = Op.getValueType();
3610  SDLoc DL(Op);
3611  SDValue Chain = Op.getOperand(0);
3612  SDValue Addr = Op.getOperand(1);
3613  unsigned Align = Op.getConstantOperandVal(3);
3614 
3615  SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3616  MachinePointerInfo(V), false, false, false, 0);
3617  Chain = VAList.getValue(1);
3618 
3619  if (Align > 8) {
3620  assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3621  VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3622  DAG.getConstant(Align - 1, getPointerTy()));
3623  VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3624  DAG.getConstant(-(int64_t)Align, getPointerTy()));
3625  }
3626 
3627  Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
3628  uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
3629 
3630  // Scalar integer and FP values smaller than 64 bits are implicitly extended
3631  // up to 64 bits. At the very least, we have to increase the striding of the
3632  // vaargs list to match this, and for FP values we need to introduce
3633  // FP_ROUND nodes as well.
3634  if (VT.isInteger() && !VT.isVector())
3635  ArgSize = 8;
3636  bool NeedFPTrunc = false;
3637  if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
3638  ArgSize = 8;
3639  NeedFPTrunc = true;
3640  }
3641 
3642  // Increment the pointer, VAList, to the next vaarg
3643  SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3644  DAG.getConstant(ArgSize, getPointerTy()));
3645  // Store the incremented VAList to the legalized pointer
3646  SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
3647  false, false, 0);
3648 
3649  // Load the actual argument out of the pointer VAList
3650  if (NeedFPTrunc) {
3651  // Load the value as an f64.
3652  SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
3653  MachinePointerInfo(), false, false, false, 0);
3654  // Round the value down to an f32.
3655  SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
3656  DAG.getIntPtrConstant(1));
3657  SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
3658  // Merge the rounded value with the chain output of the load.
3659  return DAG.getMergeValues(Ops, DL);
3660  }
3661 
3662  return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
3663  false, false, 0);
3664 }
SDValue getValue(unsigned R) const
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
getMergeValues - Create a MERGE_VALUES node from the given operands.
Type * getTypeForEVT(LLVMContext &Context) const
Definition: ValueTypes.cpp:180
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
const AArch64Subtarget * Subtarget
const DataLayout * DL
True if this is a little endian target.
virtual MVT getPointerTy(uint32_t=0) const
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
const DataLayout * getDataLayout() const
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
uint64_t getTypeAllocSize(Type *Ty) const
Definition: DataLayout.h:368
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
bool isTargetDarwin() const
uint64_t getConstantOperandVal(unsigned i) const
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
EVT getValueType() const
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
LLVM Value Representation.
Definition: Value.h:69
SDValue AArch64TargetLowering::LowerVACOPY ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3590 of file AArch64ISelLowering.cpp.

3591  {
3592  // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3593  // pointer.
3594  unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3595  const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3596  const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3597 
3598  return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3599  Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3600  8, false, false, MachinePointerInfo(DestSV),
3601  MachinePointerInfo(SrcSV));
3602 }
const AArch64Subtarget * Subtarget
const SDValue & getOperand(unsigned i) const
SDValue getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
bool isTargetDarwin() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
LLVM Value Representation.
Definition: Value.h:69
SDValue AArch64TargetLowering::LowerVASTART ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3584 of file AArch64ISelLowering.cpp.

3585  {
3586  return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3587  : LowerAAPCS_VASTART(Op, DAG);
3588 }
SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const
SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const
const AArch64Subtarget * Subtarget
bool isTargetDarwin() const
SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 4740 of file AArch64ISelLowering.cpp.

4741  {
4742  SDLoc dl(Op);
4743  EVT VT = Op.getValueType();
4744 
4745  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4746 
4747  // Convert shuffles that are directly supported on NEON to target-specific
4748  // DAG nodes, instead of keeping them as shuffles and matching them again
4749  // during code selection. This is more efficient and avoids the possibility
4750  // of inconsistencies between legalization and selection.
4751  ArrayRef<int> ShuffleMask = SVN->getMask();
4752 
4753  SDValue V1 = Op.getOperand(0);
4754  SDValue V2 = Op.getOperand(1);
4755 
4756  if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
4757  V1.getValueType().getSimpleVT())) {
4758  int Lane = SVN->getSplatIndex();
4759  // If this is undef splat, generate it via "just" vdup, if possible.
4760  if (Lane == -1)
4761  Lane = 0;
4762 
4763  if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
4764  return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
4765  V1.getOperand(0));
4766  // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
4767  // constant. If so, we can just reference the lane's definition directly.
4768  if (V1.getOpcode() == ISD::BUILD_VECTOR &&
4769  !isa<ConstantSDNode>(V1.getOperand(Lane)))
4770  return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
4771 
4772  // Otherwise, duplicate from the lane of the input vector.
4773  unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
4774 
4775  // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
4776  // to make a vector of the same size as this SHUFFLE. We can ignore the
4777  // extract entirely, and canonicalise the concat using WidenVector.
4778  if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
4779  Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
4780  V1 = V1.getOperand(0);
4781  } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
4782  unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
4783  Lane -= Idx * VT.getVectorNumElements() / 2;
4784  V1 = WidenVector(V1.getOperand(Idx), DAG);
4785  } else if (VT.getSizeInBits() == 64)
4786  V1 = WidenVector(V1, DAG);
4787 
4788  return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
4789  }
4790 
4791  if (isREVMask(ShuffleMask, VT, 64))
4792  return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
4793  if (isREVMask(ShuffleMask, VT, 32))
4794  return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
4795  if (isREVMask(ShuffleMask, VT, 16))
4796  return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
4797 
4798  bool ReverseEXT = false;
4799  unsigned Imm;
4800  if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
4801  if (ReverseEXT)
4802  std::swap(V1, V2);
4803  Imm *= getExtFactor(V1);
4804  return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
4805  DAG.getConstant(Imm, MVT::i32));
4806  } else if (V2->getOpcode() == ISD::UNDEF &&
4807  isSingletonEXTMask(ShuffleMask, VT, Imm)) {
4808  Imm *= getExtFactor(V1);
4809  return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
4810  DAG.getConstant(Imm, MVT::i32));
4811  }
4812 
4813  unsigned WhichResult;
4814  if (isZIPMask(ShuffleMask, VT, WhichResult)) {
4815  unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4816  return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4817  }
4818  if (isUZPMask(ShuffleMask, VT, WhichResult)) {
4819  unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4820  return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4821  }
4822  if (isTRNMask(ShuffleMask, VT, WhichResult)) {
4823  unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
4824  return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4825  }
4826 
4827  if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4828  unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4829  return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4830  }
4831  if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4832  unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4833  return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4834  }
4835  if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4836  unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
4837  return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4838  }
4839 
4840  SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
4841  if (Concat.getNode())
4842  return Concat;
4843 
4844  bool DstIsLeft;
4845  int Anomaly;
4846  int NumInputElements = V1.getValueType().getVectorNumElements();
4847  if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
4848  SDValue DstVec = DstIsLeft ? V1 : V2;
4849  SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
4850 
4851  SDValue SrcVec = V1;
4852  int SrcLane = ShuffleMask[Anomaly];
4853  if (SrcLane >= NumInputElements) {
4854  SrcVec = V2;
4855  SrcLane -= VT.getVectorNumElements();
4856  }
4857  SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
4858 
4859  EVT ScalarVT = VT.getVectorElementType();
4860  if (ScalarVT.getSizeInBits() < 32)
4861  ScalarVT = MVT::i32;
4862 
4863  return DAG.getNode(
4864  ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
4865  DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
4866  DstLaneV);
4867  }
4868 
4869  // If the shuffle is not directly supported and it has 4 elements, use
4870  // the PerfectShuffle-generated table to synthesize it from other shuffles.
4871  unsigned NumElts = VT.getVectorNumElements();
4872  if (NumElts == 4) {
4873  unsigned PFIndexes[4];
4874  for (unsigned i = 0; i != 4; ++i) {
4875  if (ShuffleMask[i] < 0)
4876  PFIndexes[i] = 8;
4877  else
4878  PFIndexes[i] = ShuffleMask[i];
4879  }
4880 
4881  // Compute the index in the perfect shuffle table.
4882  unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
4883  PFIndexes[2] * 9 + PFIndexes[3];
4884  unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4885  unsigned Cost = (PFEntry >> 30);
4886 
4887  if (Cost <= 4)
4888  return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4889  }
4890 
4891  return GenerateTBL(Op, ShuffleMask, DAG);
4892 }
static bool isUZP_v_undef_Mask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool isUZPMask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool isTRN_v_undef_Mask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool isINSMask(ArrayRef< int > M, int NumInputElements, bool &DstIsLeft, int &Anomaly)
static bool isZIP_v_undef_Mask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static unsigned getDUPLANEOp(EVT EltType)
static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG)
static bool isTRNMask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
EVT getVectorElementType() const
Definition: ValueTypes.h:217
static const unsigned PerfectShuffleTable[6561+1]
static bool isEXTMask(ArrayRef< int > M, EVT VT, bool &ReverseEXT, unsigned &Imm)
static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG)
static bool isREVMask(ArrayRef< int > M, EVT VT, unsigned BlockSize)
UNDEF - An undefined node.
Definition: ISDOpcodes.h:159
SDNode * getNode() const
get the SDNode which holds the desired result
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
static bool isSingletonEXTMask(ArrayRef< int > M, EVT VT, unsigned &Imm)
static SDValue GenerateTBL(SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
ArrayRef< int > getMask() const
static unsigned getExtFactor(SDValue &V)
static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl)
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:590
static bool isZIPMask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
static bool isSplatMask(const int *Mask, EVT VT)
MVT getSimpleVT() const
Definition: ValueTypes.h:204
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
SDValue AArch64TargetLowering::LowerVectorAND ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 4916 of file AArch64ISelLowering.cpp.

4917  {
4918  BuildVectorSDNode *BVN =
4920  SDValue LHS = Op.getOperand(0);
4921  SDLoc dl(Op);
4922  EVT VT = Op.getValueType();
4923 
4924  if (!BVN)
4925  return Op;
4926 
4927  APInt CnstBits(VT.getSizeInBits(), 0);
4928  APInt UndefBits(VT.getSizeInBits(), 0);
4929  if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
4930  // We only have BIC vector immediate instruction, which is and-not.
4931  CnstBits = ~CnstBits;
4932 
4933  // We make use of a little bit of goto ickiness in order to avoid having to
4934  // duplicate the immediate matching logic for the undef toggled case.
4935  bool SecondTry = false;
4936  AttemptModImm:
4937 
4938  if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
4939  CnstBits = CnstBits.zextOrTrunc(64);
4940  uint64_t CnstVal = CnstBits.getZExtValue();
4941 
4942  if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
4943  CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
4944  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4945  SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4946  DAG.getConstant(CnstVal, MVT::i32),
4947  DAG.getConstant(0, MVT::i32));
4948  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4949  }
4950 
4951  if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
4952  CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
4953  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4954  SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4955  DAG.getConstant(CnstVal, MVT::i32),
4956  DAG.getConstant(8, MVT::i32));
4957  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4958  }
4959 
4960  if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
4961  CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
4962  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4963  SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4964  DAG.getConstant(CnstVal, MVT::i32),
4965  DAG.getConstant(16, MVT::i32));
4966  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4967  }
4968 
4969  if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
4970  CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
4971  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4972  SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4973  DAG.getConstant(CnstVal, MVT::i32),
4974  DAG.getConstant(24, MVT::i32));
4975  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4976  }
4977 
4978  if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
4979  CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
4980  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4981  SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4982  DAG.getConstant(CnstVal, MVT::i32),
4983  DAG.getConstant(0, MVT::i32));
4984  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4985  }
4986 
4987  if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
4988  CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
4989  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4990  SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4991  DAG.getConstant(CnstVal, MVT::i32),
4992  DAG.getConstant(8, MVT::i32));
4993  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4994  }
4995  }
4996 
4997  if (SecondTry)
4998  goto FailedModImm;
4999  SecondTry = true;
5000  CnstBits = ~UndefBits;
5001  goto AttemptModImm;
5002  }
5003 
5004 // We can always fall back to a non-immediate AND.
5005 FailedModImm:
5006  return Op;
5007 }
static bool isAdvSIMDModImmType6(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType3(uint64_t Imm)
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1302
static bool isAdvSIMDModImmType4(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType1(uint64_t Imm)
static bool isAdvSIMDModImmType3(uint64_t Imm)
APInt LLVM_ATTRIBUTE_UNUSED_RESULT zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
Definition: APInt.cpp:1003
static uint8_t encodeAdvSIMDModImmType6(uint64_t Imm)
static bool isAdvSIMDModImmType5(uint64_t Imm)
static bool isAdvSIMDModImmType2(uint64_t Imm)
SDNode * getNode() const
get the SDNode which holds the desired result
const SDValue & getOperand(unsigned i) const
static bool isAdvSIMDModImmType1(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType2(uint64_t Imm)
Class for arbitrary precision integers.
Definition: APInt.h:75
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
static uint8_t encodeAdvSIMDModImmType5(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType4(uint64_t Imm)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits, APInt &UndefBits)
SDValue AArch64TargetLowering::LowerVectorOR ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5107 of file AArch64ISelLowering.cpp.

5108  {
5109  // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5111  SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5112  if (Res.getNode())
5113  return Res;
5114  }
5115 
5116  BuildVectorSDNode *BVN =
5118  SDValue LHS = Op.getOperand(1);
5119  SDLoc dl(Op);
5120  EVT VT = Op.getValueType();
5121 
5122  // OR commutes, so try swapping the operands.
5123  if (!BVN) {
5124  LHS = Op.getOperand(0);
5125  BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5126  }
5127  if (!BVN)
5128  return Op;
5129 
5130  APInt CnstBits(VT.getSizeInBits(), 0);
5131  APInt UndefBits(VT.getSizeInBits(), 0);
5132  if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5133  // We make use of a little bit of goto ickiness in order to avoid having to
5134  // duplicate the immediate matching logic for the undef toggled case.
5135  bool SecondTry = false;
5136  AttemptModImm:
5137 
5138  if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5139  CnstBits = CnstBits.zextOrTrunc(64);
5140  uint64_t CnstVal = CnstBits.getZExtValue();
5141 
5142  if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5143  CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5144  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5145  SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5146  DAG.getConstant(CnstVal, MVT::i32),
5147  DAG.getConstant(0, MVT::i32));
5148  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5149  }
5150 
5151  if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5152  CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5153  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5154  SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5155  DAG.getConstant(CnstVal, MVT::i32),
5156  DAG.getConstant(8, MVT::i32));
5157  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5158  }
5159 
5160  if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5161  CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5162  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5163  SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5164  DAG.getConstant(CnstVal, MVT::i32),
5165  DAG.getConstant(16, MVT::i32));
5166  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5167  }
5168 
5169  if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5170  CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5171  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5172  SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5173  DAG.getConstant(CnstVal, MVT::i32),
5174  DAG.getConstant(24, MVT::i32));
5175  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5176  }
5177 
5178  if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5179  CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5180  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5181  SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5182  DAG.getConstant(CnstVal, MVT::i32),
5183  DAG.getConstant(0, MVT::i32));
5184  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5185  }
5186 
5187  if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5188  CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5189  MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5190  SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5191  DAG.getConstant(CnstVal, MVT::i32),
5192  DAG.getConstant(8, MVT::i32));
5193  return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5194  }
5195  }
5196 
5197  if (SecondTry)
5198  goto FailedModImm;
5199  SecondTry = true;
5200  CnstBits = UndefBits;
5201  goto AttemptModImm;
5202  }
5203 
5204 // We can always fall back to a non-immediate OR.
5205 FailedModImm:
5206  return Op;
5207 }
static bool isAdvSIMDModImmType6(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType3(uint64_t Imm)
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1302
static bool isAdvSIMDModImmType4(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType1(uint64_t Imm)
static bool isAdvSIMDModImmType3(uint64_t Imm)
APInt LLVM_ATTRIBUTE_UNUSED_RESULT zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
Definition: APInt.cpp:1003
static uint8_t encodeAdvSIMDModImmType6(uint64_t Imm)
static bool isAdvSIMDModImmType5(uint64_t Imm)
static bool isAdvSIMDModImmType2(uint64_t Imm)
SDNode * getNode() const
get the SDNode which holds the desired result
const SDValue & getOperand(unsigned i) const
static bool isAdvSIMDModImmType1(uint64_t Imm)
static cl::opt< bool > EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden, cl::desc("Allow AArch64 SLI/SRI formation"), cl::init(false))
static uint8_t encodeAdvSIMDModImmType2(uint64_t Imm)
Class for arbitrary precision integers.
Definition: APInt.h:75
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
static uint8_t encodeAdvSIMDModImmType5(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType4(uint64_t Imm)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits, APInt &UndefBits)
static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG)
SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5801 of file AArch64ISelLowering.cpp.

5802  {
5803  EVT VT = Op.getValueType();
5804  SDLoc DL(Op);
5805  int64_t Cnt;
5806 
5807  if (!Op.getOperand(1).getValueType().isVector())
5808  return Op;
5809  unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5810 
5811  switch (Op.getOpcode()) {
5812  default:
5813  llvm_unreachable("unexpected shift opcode");
5814 
5815  case ISD::SHL:
5816  if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
5817  return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
5818  DAG.getConstant(Cnt, MVT::i32));
5819  return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5820  DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
5821  Op.getOperand(0), Op.getOperand(1));
5822  case ISD::SRA:
5823  case ISD::SRL:
5824  // Right shift immediate
5825  if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
5826  Cnt < EltSize) {
5827  unsigned Opc =
5829  return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
5830  DAG.getConstant(Cnt, MVT::i32));
5831  }
5832 
5833  // Right shift register. Note, there is not a shift right register
5834  // instruction, but the shift left register instruction takes a signed
5835  // value, where negative numbers specify a right shift.
5836  unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
5837  : Intrinsic::aarch64_neon_ushl;
5838  // negate the shift amount
5839  SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
5840  SDValue NegShiftLeft =
5842  DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
5843  return NegShiftLeft;
5844  }
5845 
5846  return SDValue();
5847 }
static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt)
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, int64_t &Cnt)
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
const DataLayout * DL
True if this is a little endian target.
EVT getVectorElementType() const
Definition: ValueTypes.h:217
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue AArch64TargetLowering::LowerVSETCC ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5942 of file AArch64ISelLowering.cpp.

5943  {
5944  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5945  SDValue LHS = Op.getOperand(0);
5946  SDValue RHS = Op.getOperand(1);
5947  SDLoc dl(Op);
5948 
5950  assert(LHS.getValueType() == RHS.getValueType());
5952  return EmitVectorComparison(LHS, RHS, AArch64CC, false, Op.getValueType(),
5953  dl, DAG);
5954  }
5955 
5958 
5959  // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
5960  // clean. Some of them require two branches to implement.
5961  AArch64CC::CondCode CC1, CC2;
5962  bool ShouldInvert;
5963  changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
5964 
5965  bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
5966  SDValue Cmp =
5967  EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG);
5968  if (!Cmp.getNode())
5969  return SDValue();
5970 
5971  if (CC2 != AArch64CC::AL) {
5972  SDValue Cmp2 =
5973  EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG);
5974  if (!Cmp2.getNode())
5975  return SDValue();
5976 
5977  Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2);
5978  }
5979 
5980  if (ShouldInvert)
5981  return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
5982 
5983  return Cmp;
5984 }
const TargetMachine & getTargetMachine() const
static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS, AArch64CC::CondCode CC, bool NoNans, EVT VT, SDLoc dl, SelectionDAG &DAG)
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
EVT getVectorElementType() const
Definition: ValueTypes.h:217
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
SDValue getNOT(SDLoc DL, SDValue Val, EVT VT)
getNOT - Create a bitwise NOT operation as (XOR Val, -1).
static void changeVectorFPCCToAArch64CC(ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2, bool &Invert)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC)
const char * TargetLowering::LowerXConstraint ( EVT  ConstraintVT) const
virtualinherited

Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand. This returns null if there is no replacement to make.

LowerXConstraint - try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2091 of file TargetLowering.cpp.

2091  {
2092  if (ConstraintVT.isInteger())
2093  return "r";
2094  if (ConstraintVT.isFloatingPoint())
2095  return "f"; // works for many targets
2096  return nullptr;
2097 }
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
std::pair< SDValue, SDValue > TargetLowering::makeLibCall ( SelectionDAG DAG,
RTLIB::Libcall  LC,
EVT  RetVT,
const SDValue Ops,
unsigned  NumOps,
bool  isSigned,
SDLoc  dl,
bool  doesNotReturn = false,
bool  isReturnValueUsed = true 
) const
inherited

Returns a pair of (return value, chain).

Generate a libcall taking the given operands as arguments and returning a result of type RetVT.

Definition at line 86 of file TargetLowering.cpp.

91  {
93  Args.reserve(NumOps);
94 
96  for (unsigned i = 0; i != NumOps; ++i) {
97  Entry.Node = Ops[i];
98  Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
99  Entry.isSExt = isSigned;
100  Entry.isZExt = !isSigned;
101  Args.push_back(Entry);
102  }
104 
105  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
107  CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
108  .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
109  .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed)
110  .setSExtResult(isSigned).setZExtResult(!isSigned);
111  return LowerCallTo(CLI);
112 }
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
Type * getTypeForEVT(LLVMContext &Context) const
Definition: ValueTypes.cpp:180
SDValue getExternalSymbol(const char *Sym, EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
std::vector< ArgListEntry > ArgListTy
const char * Args[]
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
EVT getValueType() const
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
bool AArch64TargetLowering::mayBeEmittedAsTailCall ( CallInst CI) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 7893 of file AArch64ISelLowering.cpp.

7893  {
7894  if (!CI->isTailCall())
7895  return false;
7896 
7897  return true;
7898 }
bool isTailCall() const
TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints ( ImmutableCallSite  CS) const
virtualinherited

Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. If this returns an empty vector, and if the constraint string itself isn't empty, there was an error parsing.

ParseConstraints - Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. If this returns an empty vector, and if the constraint string itself isn't empty, there was an error parsing.

ConstraintOperands - Information about all of the constraints.

Definition at line 2233 of file TargetLowering.cpp.

2234  {
2235  /// ConstraintOperands - Information about all of the constraints.
2236  AsmOperandInfoVector ConstraintOperands;
2237  const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2238  unsigned maCount = 0; // Largest number of multiple alternative constraints.
2239 
2240  // Do a prepass over the constraints, canonicalizing them, and building up the
2241  // ConstraintOperands list.
2243  ConstraintInfos = IA->ParseConstraints();
2244 
2245  unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2246  unsigned ResNo = 0; // ResNo - The result number of the next output.
2247 
2248  for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2249  ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2250  AsmOperandInfo &OpInfo = ConstraintOperands.back();
2251 
2252  // Update multiple alternative constraint count.
2253  if (OpInfo.multipleAlternatives.size() > maCount)
2254  maCount = OpInfo.multipleAlternatives.size();
2255 
2256  OpInfo.ConstraintVT = MVT::Other;
2257 
2258  // Compute the value type for each operand.
2259  switch (OpInfo.Type) {
2260  case InlineAsm::isOutput:
2261  // Indirect outputs just consume an argument.
2262  if (OpInfo.isIndirect) {
2263  OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2264  break;
2265  }
2266 
2267  // The return value of the call is this value. As such, there is no
2268  // corresponding argument.
2269  assert(!CS.getType()->isVoidTy() &&
2270  "Bad inline asm!");
2271  if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2272  OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
2273  } else {
2274  assert(ResNo == 0 && "Asm only has one result!");
2275  OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
2276  }
2277  ++ResNo;
2278  break;
2279  case InlineAsm::isInput:
2280  OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2281  break;
2282  case InlineAsm::isClobber:
2283  // Nothing to do.
2284  break;
2285  }
2286 
2287  if (OpInfo.CallOperandVal) {
2288  llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2289  if (OpInfo.isIndirect) {
2290  llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2291  if (!PtrTy)
2292  report_fatal_error("Indirect operand for inline asm not a pointer!");
2293  OpTy = PtrTy->getElementType();
2294  }
2295 
2296  // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2297  if (StructType *STy = dyn_cast<StructType>(OpTy))
2298  if (STy->getNumElements() == 1)
2299  OpTy = STy->getElementType(0);
2300 
2301  // If OpTy is not a single value, it may be a struct/union that we
2302  // can tile with integers.
2303  if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2304  unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy);
2305  switch (BitSize) {
2306  default: break;
2307  case 1:
2308  case 8:
2309  case 16:
2310  case 32:
2311  case 64:
2312  case 128:
2313  OpInfo.ConstraintVT =
2314  MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2315  break;
2316  }
2317  } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2318  unsigned PtrSize
2319  = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace());
2320  OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
2321  } else {
2322  OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2323  }
2324  }
2325  }
2326 
2327  // If we have multiple alternative constraints, select the best alternative.
2328  if (ConstraintInfos.size()) {
2329  if (maCount) {
2330  unsigned bestMAIndex = 0;
2331  int bestWeight = -1;
2332  // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2333  int weight = -1;
2334  unsigned maIndex;
2335  // Compute the sums of the weights for each alternative, keeping track
2336  // of the best (highest weight) one so far.
2337  for (maIndex = 0; maIndex < maCount; ++maIndex) {
2338  int weightSum = 0;
2339  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2340  cIndex != eIndex; ++cIndex) {
2341  AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2342  if (OpInfo.Type == InlineAsm::isClobber)
2343  continue;
2344 
2345  // If this is an output operand with a matching input operand,
2346  // look up the matching input. If their types mismatch, e.g. one
2347  // is an integer, the other is floating point, or their sizes are
2348  // different, flag it as an maCantMatch.
2349  if (OpInfo.hasMatchingInput()) {
2350  AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2351  if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2352  if ((OpInfo.ConstraintVT.isInteger() !=
2353  Input.ConstraintVT.isInteger()) ||
2354  (OpInfo.ConstraintVT.getSizeInBits() !=
2355  Input.ConstraintVT.getSizeInBits())) {
2356  weightSum = -1; // Can't match.
2357  break;
2358  }
2359  }
2360  }
2361  weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2362  if (weight == -1) {
2363  weightSum = -1;
2364  break;
2365  }
2366  weightSum += weight;
2367  }
2368  // Update best.
2369  if (weightSum > bestWeight) {
2370  bestWeight = weightSum;
2371  bestMAIndex = maIndex;
2372  }
2373  }
2374 
2375  // Now select chosen alternative in each constraint.
2376  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2377  cIndex != eIndex; ++cIndex) {
2378  AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2379  if (cInfo.Type == InlineAsm::isClobber)
2380  continue;
2381  cInfo.selectAlternative(bestMAIndex);
2382  }
2383  }
2384  }
2385 
2386  // Check and hook up tied operands, choose constraint code to use.
2387  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2388  cIndex != eIndex; ++cIndex) {
2389  AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2390 
2391  // If this is an output operand with a matching input operand, look up the
2392  // matching input. If their types mismatch, e.g. one is an integer, the
2393  // other is floating point, or their sizes are different, flag it as an
2394  // error.
2395  if (OpInfo.hasMatchingInput()) {
2396  AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2397 
2398  if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2399  std::pair<unsigned, const TargetRegisterClass*> MatchRC =
2400  getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
2401  OpInfo.ConstraintVT);
2402  std::pair<unsigned, const TargetRegisterClass*> InputRC =
2403  getRegForInlineAsmConstraint(Input.ConstraintCode,
2404  Input.ConstraintVT);
2405  if ((OpInfo.ConstraintVT.isInteger() !=
2406  Input.ConstraintVT.isInteger()) ||
2407  (MatchRC.second != InputRC.second)) {
2408  report_fatal_error("Unsupported asm: input constraint"
2409  " with a matching output constraint of"
2410  " incompatible type!");
2411  }
2412  }
2413 
2414  }
2415  }
2416 
2417  return ConstraintOperands;
2418 }
static MVT getIntegerVT(unsigned BitWidth)
Type * getType() const
Definition: CallSite.h:157
ValTy * getArgument(unsigned ArgNo) const
Definition: CallSite.h:113
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
bool isSingleValueType() const
Definition: Type.h:250
MVT getSimpleValueType(Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
Definition: Type.h:125
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
ValTy * getCalledValue() const
Definition: CallSite.h:85
Type * getElementType() const
Definition: DerivedTypes.h:319
assert(Globals.size() > 1)
const DataLayout * getDataLayout() const
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Definition: ValueTypes.cpp:247
std::vector< AsmOperandInfo > AsmOperandInfoVector
static IntegerType * get(LLVMContext &C, unsigned NumBits)
Get or create an IntegerType instance.
Definition: Type.cpp:299
static cl::opt< std::string > Input(cl::Positional, cl::desc("<input>"), cl::init("-"))
bool isSized(SmallPtrSet< const Type *, 4 > *Visited=nullptr) const
Definition: Type.h:268
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
unsigned getPointerSizeInBits(unsigned AS=0) const
Definition: DataLayout.h:313
LLVM Value Representation.
Definition: Value.h:69
virtual ConstraintWeight getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const
uint64_t getTypeSizeInBits(Type *Ty) const
Definition: DataLayout.h:522
std::vector< ConstraintInfo > ConstraintInfoVector
Definition: InlineAsm.h:118
static ConstraintInfoVector ParseConstraints(StringRef ConstraintString)
Definition: InlineAsm.cpp:203
bool isVoidTy() const
isVoidTy - Return true if this is 'void'.
Definition: Type.h:137
SDValue AArch64TargetLowering::PerformDAGCombine ( SDNode N,
DAGCombinerInfo DCI 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 7780 of file AArch64ISelLowering.cpp.

7781  {
7782  SelectionDAG &DAG = DCI.DAG;
7783  switch (N->getOpcode()) {
7784  default:
7785  break;
7786  case ISD::ADD:
7787  case ISD::SUB:
7788  return performAddSubLongCombine(N, DCI, DAG);
7789  case ISD::XOR:
7790  return performXorCombine(N, DAG, DCI, Subtarget);
7791  case ISD::MUL:
7792  return performMulCombine(N, DAG, DCI, Subtarget);
7793  case ISD::SINT_TO_FP:
7794  case ISD::UINT_TO_FP:
7795  return performIntToFpCombine(N, DAG);
7796  case ISD::OR:
7797  return performORCombine(N, DCI, Subtarget);
7799  return performIntrinsicCombine(N, DCI, Subtarget);
7800  case ISD::ANY_EXTEND:
7801  case ISD::ZERO_EXTEND:
7802  case ISD::SIGN_EXTEND:
7803  return performExtendCombine(N, DCI, DAG);
7804  case ISD::BITCAST:
7805  return performBitcastCombine(N, DCI, DAG);
7806  case ISD::CONCAT_VECTORS:
7807  return performConcatVectorsCombine(N, DCI, DAG);
7808  case ISD::SELECT:
7809  return performSelectCombine(N, DAG);
7810  case ISD::VSELECT:
7811  return performVSelectCombine(N, DCI.DAG);
7812  case ISD::STORE:
7813  return performSTORECombine(N, DCI, DAG, Subtarget);
7814  case AArch64ISD::BRCOND:
7815  return performBRCONDCombine(N, DCI, DAG);
7816  case AArch64ISD::DUP:
7817  return performPostLD1Combine(N, DCI, false);
7819  return performPostLD1Combine(N, DCI, true);
7820  case ISD::INTRINSIC_VOID:
7822  switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7823  case Intrinsic::aarch64_neon_ld2:
7824  case Intrinsic::aarch64_neon_ld3:
7825  case Intrinsic::aarch64_neon_ld4:
7826  case Intrinsic::aarch64_neon_ld1x2:
7827  case Intrinsic::aarch64_neon_ld1x3:
7828  case Intrinsic::aarch64_neon_ld1x4:
7829  case Intrinsic::aarch64_neon_ld2lane:
7830  case Intrinsic::aarch64_neon_ld3lane:
7831  case Intrinsic::aarch64_neon_ld4lane:
7832  case Intrinsic::aarch64_neon_ld2r:
7833  case Intrinsic::aarch64_neon_ld3r:
7834  case Intrinsic::aarch64_neon_ld4r:
7835  case Intrinsic::aarch64_neon_st2:
7836  case Intrinsic::aarch64_neon_st3:
7837  case Intrinsic::aarch64_neon_st4:
7838  case Intrinsic::aarch64_neon_st1x2:
7839  case Intrinsic::aarch64_neon_st1x3:
7840  case Intrinsic::aarch64_neon_st1x4:
7841  case Intrinsic::aarch64_neon_st2lane:
7842  case Intrinsic::aarch64_neon_st3lane:
7843  case Intrinsic::aarch64_neon_st4lane:
7844  return performNEONPostLDSTCombine(N, DCI, DAG);
7845  default:
7846  break;
7847  }
7848  }
7849  return SDValue();
7850 }
static SDValue performBitcastCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG)
static SDValue performNEONPostLDSTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
unsigned getOpcode() const
const SDValue & getOperand(unsigned Num) const
static SDValue performExtendCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue performAddSubLongCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
const AArch64Subtarget * Subtarget
static SDValue performConcatVectorsCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
static SDValue performBRCONDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG)
static SDValue performSTORECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG)
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
static SDValue performPostLD1Combine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, bool IsLaneOp)
static SDValue performIntrinsicCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
virtual SDValue llvm::TargetLowering::prepareVolatileOrAtomicLoad ( SDValue  Chain,
SDLoc  DL,
SelectionDAG DAG 
) const
inlinevirtualinherited

This callback is used to prepare for a volatile or atomic load. It takes a chain node as input and returns the chain for the load itself.

Having a callback like this is necessary for targets like SystemZ, which allows a CPU to reuse the result of a previous load indefinitely, even if a cache-coherent store is performed by another CPU. The default implementation does nothing.

Reimplemented in llvm::SystemZTargetLowering.

Definition at line 2355 of file TargetLowering.h.

2356  {
2357  return Chain;
2358  }
SDValue AArch64TargetLowering::ReconstructShuffle ( SDValue  Op,
SelectionDAG DAG 
) const

Definition at line 4134 of file AArch64ISelLowering.cpp.

4135  {
4136  assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4137  SDLoc dl(Op);
4138  EVT VT = Op.getValueType();
4139  unsigned NumElts = VT.getVectorNumElements();
4140 
4141  SmallVector<SDValue, 2> SourceVecs;
4142  SmallVector<unsigned, 2> MinElts;
4143  SmallVector<unsigned, 2> MaxElts;
4144 
4145  for (unsigned i = 0; i < NumElts; ++i) {
4146  SDValue V = Op.getOperand(i);
4147  if (V.getOpcode() == ISD::UNDEF)
4148  continue;
4149  else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4150  // A shuffle can only come from building a vector from various
4151  // elements of other vectors.
4152  return SDValue();
4153  }
4154 
4155  // Record this extraction against the appropriate vector if possible...
4156  SDValue SourceVec = V.getOperand(0);
4157  unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4158  bool FoundSource = false;
4159  for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4160  if (SourceVecs[j] == SourceVec) {
4161  if (MinElts[j] > EltNo)
4162  MinElts[j] = EltNo;
4163  if (MaxElts[j] < EltNo)
4164  MaxElts[j] = EltNo;
4165  FoundSource = true;
4166  break;
4167  }
4168  }
4169 
4170  // Or record a new source if not...
4171  if (!FoundSource) {
4172  SourceVecs.push_back(SourceVec);
4173  MinElts.push_back(EltNo);
4174  MaxElts.push_back(EltNo);
4175  }
4176  }
4177 
4178  // Currently only do something sane when at most two source vectors
4179  // involved.
4180  if (SourceVecs.size() > 2)
4181  return SDValue();
4182 
4183  SDValue ShuffleSrcs[2] = { DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4184  int VEXTOffsets[2] = { 0, 0 };
4185  int OffsetMultipliers[2] = { 1, 1 };
4186 
4187  // This loop extracts the usage patterns of the source vectors
4188  // and prepares appropriate SDValues for a shuffle if possible.
4189  for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4190  unsigned NumSrcElts = SourceVecs[i].getValueType().getVectorNumElements();
4191  SDValue CurSource = SourceVecs[i];
4192  if (SourceVecs[i].getValueType().getVectorElementType() !=
4193  VT.getVectorElementType()) {
4194  // It may hit this case if SourceVecs[i] is AssertSext/AssertZext.
4195  // Then bitcast it to the vector which holds asserted element type,
4196  // and record the multiplier of element width between SourceVecs and
4197  // Build_vector which is needed to extract the correct lanes later.
4198  EVT CastVT =
4200  SourceVecs[i].getValueSizeInBits() /
4202 
4203  CurSource = DAG.getNode(ISD::BITCAST, dl, CastVT, SourceVecs[i]);
4204  OffsetMultipliers[i] = CastVT.getVectorNumElements() / NumSrcElts;
4205  NumSrcElts *= OffsetMultipliers[i];
4206  MaxElts[i] *= OffsetMultipliers[i];
4207  MinElts[i] *= OffsetMultipliers[i];
4208  }
4209 
4210  if (CurSource.getValueType() == VT) {
4211  // No VEXT necessary
4212  ShuffleSrcs[i] = CurSource;
4213  VEXTOffsets[i] = 0;
4214  continue;
4215  } else if (NumSrcElts < NumElts) {
4216  // We can pad out the smaller vector for free, so if it's part of a
4217  // shuffle...
4218  ShuffleSrcs[i] = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, CurSource,
4219  DAG.getUNDEF(CurSource.getValueType()));
4220  continue;
4221  }
4222 
4223  // Since only 64-bit and 128-bit vectors are legal on ARM and
4224  // we've eliminated the other cases...
4225  assert(NumSrcElts == 2 * NumElts &&
4226  "unexpected vector sizes in ReconstructShuffle");
4227 
4228  if (MaxElts[i] - MinElts[i] >= NumElts) {
4229  // Span too large for a VEXT to cope
4230  return SDValue();
4231  }
4232 
4233  if (MinElts[i] >= NumElts) {
4234  // The extraction can just take the second half
4235  VEXTOffsets[i] = NumElts;
4236  ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4237  DAG.getIntPtrConstant(NumElts));
4238  } else if (MaxElts[i] < NumElts) {
4239  // The extraction can just take the first half
4240  VEXTOffsets[i] = 0;
4241  ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4242  DAG.getIntPtrConstant(0));
4243  } else {
4244  // An actual VEXT is needed
4245  VEXTOffsets[i] = MinElts[i];
4246  SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4247  DAG.getIntPtrConstant(0));
4248  SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4249  DAG.getIntPtrConstant(NumElts));
4250  unsigned Imm = VEXTOffsets[i] * getExtFactor(VEXTSrc1);
4251  ShuffleSrcs[i] = DAG.getNode(AArch64ISD::EXT, dl, VT, VEXTSrc1, VEXTSrc2,
4252  DAG.getConstant(Imm, MVT::i32));
4253  }
4254  }
4255 
4256  SmallVector<int, 8> Mask;
4257 
4258  for (unsigned i = 0; i < NumElts; ++i) {
4259  SDValue Entry = Op.getOperand(i);
4260  if (Entry.getOpcode() == ISD::UNDEF) {
4261  Mask.push_back(-1);
4262  continue;
4263  }
4264 
4265  SDValue ExtractVec = Entry.getOperand(0);
4266  int ExtractElt =
4267  cast<ConstantSDNode>(Op.getOperand(i).getOperand(1))->getSExtValue();
4268  if (ExtractVec == SourceVecs[0]) {
4269  Mask.push_back(ExtractElt * OffsetMultipliers[0] - VEXTOffsets[0]);
4270  } else {
4271  Mask.push_back(ExtractElt * OffsetMultipliers[1] + NumElts -
4272  VEXTOffsets[1]);
4273  }
4274  }
4275 
4276  // Final check before we try to produce nonsense...
4277  if (isShuffleMaskLegal(Mask, VT))
4278  return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4279  &Mask[0]);
4280 
4281  return SDValue();
4282 }
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
EVT getVectorElementType() const
Definition: ValueTypes.h:217
SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2, const int *MaskElts)
SDValue getUNDEF(EVT VT)
getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:625
UNDEF - An undefined node.
Definition: ISDOpcodes.h:159
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
static unsigned getExtFactor(SDValue &V)
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
bool isShuffleMaskLegal(const SmallVectorImpl< int > &M, EVT VT) const override
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
void AArch64TargetLowering::ReplaceNodeResults ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 7987 of file AArch64ISelLowering.cpp.

7988  {
7989  switch (N->getOpcode()) {
7990  default:
7991  llvm_unreachable("Don't know how to custom expand this");
7992  case ISD::BITCAST:
7993  ReplaceBITCASTResults(N, Results, DAG);
7994  return;
7995  case ISD::FP_TO_UINT:
7996  case ISD::FP_TO_SINT:
7997  assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
7998  // Let normal code take care of it by not adding anything to Results.
7999  return;
8000  }
8001 }
unsigned getOpcode() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
EVT getValueType(unsigned ResNo) const
assert(Globals.size() > 1)
static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
virtual void llvm::TargetLoweringBase::resetOperationActions ( )
inlinevirtualinherited

Reset the operation actions based on target options.

Reimplemented in llvm::X86TargetLowering.

Definition at line 959 of file TargetLowering.h.

959 {}
void AArch64TargetLowering::saveVarArgRegisters ( CCState CCInfo,
SelectionDAG DAG,
SDLoc  DL,
SDValue Chain 
) const
private

Definition at line 1859 of file AArch64ISelLowering.cpp.

1861  {
1862  MachineFunction &MF = DAG.getMachineFunction();
1863  MachineFrameInfo *MFI = MF.getFrameInfo();
1865 
1866  SmallVector<SDValue, 8> MemOps;
1867 
1868  static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
1869  AArch64::X3, AArch64::X4, AArch64::X5,
1870  AArch64::X6, AArch64::X7 };
1871  static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
1872  unsigned FirstVariadicGPR =
1873  CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs);
1874 
1875  unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
1876  int GPRIdx = 0;
1877  if (GPRSaveSize != 0) {
1878  GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
1879 
1880  SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
1881 
1882  for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
1883  unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
1884  SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
1885  SDValue Store =
1886  DAG.getStore(Val.getValue(1), DL, Val, FIN,
1887  MachinePointerInfo::getStack(i * 8), false, false, 0);
1888  MemOps.push_back(Store);
1889  FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1890  DAG.getConstant(8, getPointerTy()));
1891  }
1892  }
1893  FuncInfo->setVarArgsGPRIndex(GPRIdx);
1894  FuncInfo->setVarArgsGPRSize(GPRSaveSize);
1895 
1896  if (Subtarget->hasFPARMv8()) {
1897  static const MCPhysReg FPRArgRegs[] = {
1898  AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
1899  AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
1900  static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
1901  unsigned FirstVariadicFPR =
1902  CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs);
1903 
1904  unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
1905  int FPRIdx = 0;
1906  if (FPRSaveSize != 0) {
1907  FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
1908 
1909  SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
1910 
1911  for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
1912  unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
1913  SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
1914 
1915  SDValue Store =
1916  DAG.getStore(Val.getValue(1), DL, Val, FIN,
1917  MachinePointerInfo::getStack(i * 16), false, false, 0);
1918  MemOps.push_back(Store);
1919  FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1920  DAG.getConstant(16, getPointerTy()));
1921  }
1922  }
1923  FuncInfo->setVarArgsFPRIndex(FPRIdx);
1924  FuncInfo->setVarArgsFPRSize(FPRSaveSize);
1925  }
1926 
1927  if (!MemOps.empty()) {
1928  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
1929  }
1930 }
SDValue getValue(unsigned R) const
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
const AArch64Subtarget * Subtarget
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
Abstract Stack Frame Information.
const DataLayout * DL
True if this is a little endian target.
virtual MVT getPointerTy(uint32_t=0) const
uint16_t MCPhysReg
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
unsigned getFirstUnallocated(const MCPhysReg *Regs, unsigned NumRegs) const
static const MCPhysReg GPRArgRegs[]
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
MachineFrameInfo * getFrameInfo()
static MachinePointerInfo getStack(int64_t Offset)
getStack - stack pointer relative access.
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void llvm::TargetLoweringBase::setBooleanContents ( BooleanContent  Ty)
inlineprotectedinherited

Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. See getBooleanContents.

Definition at line 964 of file TargetLowering.h.

964  {
965  BooleanContents = Ty;
967  }
BooleanContent BooleanFloatContents
BooleanContent BooleanContents
void llvm::TargetLoweringBase::setBooleanContents ( BooleanContent  IntTy,
BooleanContent  FloatTy 
)
inlineprotectedinherited

Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. See getBooleanContents.

Definition at line 971 of file TargetLowering.h.

971  {
972  BooleanContents = IntTy;
973  BooleanFloatContents = FloatTy;
974  }
BooleanContent BooleanFloatContents
BooleanContent BooleanContents
void llvm::TargetLoweringBase::setBooleanVectorContents ( BooleanContent  Ty)
inlineprotectedinherited

Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. See getBooleanContents.

Definition at line 978 of file TargetLowering.h.

978  {
980  }
BooleanContent BooleanVectorContents
void llvm::TargetLoweringBase::setCmpLibcallCC ( RTLIB::Libcall  Call,
ISD::CondCode  CC 
)
inlineinherited

Override the default CondCode to be used to test the result of the comparison libcall against zero.

Definition at line 1431 of file TargetLowering.h.

1431  {
1432  CmpLibcallCCs[Call] = CC;
1433  }
ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]
void llvm::TargetLoweringBase::setCondCodeAction ( ISD::CondCode  CC,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it.

The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit value and the upper 27 bits index into the second dimension of the array to select what 32-bit value to use.

Definition at line 1156 of file TargetLowering.h.

1157  {
1158  assert(VT < MVT::LAST_VALUETYPE &&
1159  (unsigned)CC < array_lengthof(CondCodeActions) &&
1160  "Table isn't big enough!");
1161  /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1162  /// value and the upper 27 bits index into the second dimension of the array
1163  /// to select what 32-bit value to use.
1164  uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1165  CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1166  CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1167  }
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE+15)/16]
void llvm::TargetLoweringBase::setExceptionPointerRegister ( unsigned  R)
inlineprotectedinherited

If set to a physical register, this sets the register that receives the exception address on entry to a landing pad.

Definition at line 1018 of file TargetLowering.h.

1018  {
1020  }
void llvm::TargetLoweringBase::setExceptionSelectorRegister ( unsigned  R)
inlineprotectedinherited

If set to a physical register, this sets the register that receives the exception typeid on entry to a landing pad.

Definition at line 1024 of file TargetLowering.h.

1024  {
1026  }
void llvm::TargetLoweringBase::setHasExtractBitsInsn ( bool  hasExtractInsn = true)
inlineprotectedinherited

Tells the code generator that the target has BitExtract instructions. The code generator will aggressively sink "shift"s into the blocks of their users if the users will generate "and" instructions which can be combined with "shift" to BitExtract instructions.

Definition at line 1047 of file TargetLowering.h.

1047  {
1048  HasExtractBitsInsn = hasExtractInsn;
1049  }
void llvm::TargetLoweringBase::setHasMultipleConditionRegisters ( bool  hasManyRegs = true)
inlineprotectedinherited

Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. With multiple condition registers, the code generator will not aggressively sink comparisons into the blocks of their users.

Definition at line 1039 of file TargetLowering.h.

1039  {
1040  HasMultipleConditionRegisters = hasManyRegs;
1041  }
void llvm::TargetLoweringBase::setIndexedLoadAction ( unsigned  IdxMode,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it.

NOTE: All indexed mode loads are initialized to Expand in TargetLowering.cpp

Definition at line 1131 of file TargetLowering.h.

1132  {
1134  (unsigned)Action < 0xf && "Table isn't big enough!");
1135  // Load action are kept in the upper half.
1136  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1137  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1138  }
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
assert(Globals.size() > 1)
void llvm::TargetLoweringBase::setIndexedStoreAction ( unsigned  IdxMode,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it.

NOTE: All indexed mode stores are initialized to Expand in TargetLowering.cpp

Definition at line 1145 of file TargetLowering.h.

1146  {
1148  (unsigned)Action < 0xf && "Table isn't big enough!");
1149  // Store action are kept in the lower half.
1150  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1151  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1152  }
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
assert(Globals.size() > 1)
void llvm::TargetLoweringBase::setInsertFencesForAtomic ( bool  fence)
inlineprotectedinherited

Set if the DAG builder should automatically insert fences and reduce the order of atomic memory operations to Monotonic.

Definition at line 1222 of file TargetLowering.h.

1222  {
1223  InsertFencesForAtomic = fence;
1224  }
void llvm::TargetLoweringBase::setIntDivIsCheap ( bool  isCheap = true)
inlineprotectedinherited

Tells the code generator that integer divide is expensive, and if possible, should be replaced by an alternate sequence of instructions not containing an integer divide.

Definition at line 1060 of file TargetLowering.h.

1060 { IntDivIsCheap = isCheap; }
void llvm::TargetLoweringBase::setJumpBufAlignment ( unsigned  Align)
inlineprotectedinherited

Set the target's required jmp_buf buffer alignment (in bytes); default is 0

Definition at line 1192 of file TargetLowering.h.

1192  {
1194  }
unsigned JumpBufAlignment
The alignment, in bytes, of the target's jmp_buf buffers.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setJumpBufSize ( unsigned  Size)
inlineprotectedinherited

Set the target's required jmp_buf buffer size (in bytes); default is 200.

Definition at line 1186 of file TargetLowering.h.

1186  {
1187  JumpBufSize = Size;
1188  }
unsigned JumpBufSize
The size, in bytes, of the target's jmp_buf buffers.
void llvm::TargetLoweringBase::setJumpIsExpensive ( bool  isExpensive = true)
inlineprotectedinherited

Tells the code generator not to expand sequence of operations into a separate sequences that increases the amount of flow control.

Definition at line 1053 of file TargetLowering.h.

1053  {
1054  JumpIsExpensive = isExpensive;
1055  }
void llvm::TargetLoweringBase::setLibcallCallingConv ( RTLIB::Libcall  Call,
CallingConv::ID  CC 
)
inlineinherited

Set the CallingConv that should be used for the specified libcall.

Definition at line 1442 of file TargetLowering.h.

1442  {
1443  LibcallCallingConvs[Call] = CC;
1444  }
CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]
Stores the CallingConv that should be used for each libcall.
void llvm::TargetLoweringBase::setLibcallName ( RTLIB::Libcall  Call,
const char *  Name 
)
inlineinherited

Rename the default libcall routine name for the specified libcall.

Definition at line 1420 of file TargetLowering.h.

1420  {
1422  }
const char * LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]
Stores the name each libcall.
void llvm::TargetLoweringBase::setLoadExtAction ( unsigned  ExtType,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified load with extension does not work with the specified type and indicate what to do about it.

Definition at line 1110 of file TargetLowering.h.

1111  {
1113  "Table isn't big enough!");
1114  LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1115  }
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
assert(Globals.size() > 1)
uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]
void llvm::TargetLoweringBase::setMinFunctionAlignment ( unsigned  Align)
inlineprotectedinherited

Set the target's minimum function alignment (in log2(bytes))

Definition at line 1197 of file TargetLowering.h.

1197  {
1199  }
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setMinimumJumpTableEntries ( int  Val)
inlineprotectedinherited

Indicate the number of blocks to generate jump tables rather than if sequence.

Definition at line 1006 of file TargetLowering.h.

1006  {
1008  }
int MinimumJumpTableEntries
Number of blocks threshold to use jump tables.
void llvm::TargetLoweringBase::setMinStackArgumentAlignment ( unsigned  Align)
inlineprotectedinherited

Set the minimum stack alignment of an argument (in log2(bytes)).

Definition at line 1216 of file TargetLowering.h.

1216  {
1218  }
unsigned MinStackArgumentAlignment
The minimum alignment that any argument on the stack needs to have.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setOperationAction ( unsigned  Op,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified operation does not work with the specified type and indicate what to do about it.

Definition at line 1102 of file TargetLowering.h.

1103  {
1104  assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1105  OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1106  }
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]
void llvm::TargetLoweringBase::setPow2DivIsCheap ( bool  isCheap = true)
inlineprotectedinherited

Tells the code generator that it shouldn't generate srl/add/sra for a signed divide by power of two, and let the target handle it.

Definition at line 1069 of file TargetLowering.h.

1069 { Pow2DivIsCheap = isCheap; }
void llvm::TargetLoweringBase::setPrefFunctionAlignment ( unsigned  Align)
inlineprotectedinherited

Set the target's preferred function alignment. This should be set if there is a performance benefit to higher-than-minimum alignment (in log2(bytes))

Definition at line 1204 of file TargetLowering.h.

1204  {
1206  }
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setPrefLoopAlignment ( unsigned  Align)
inlineprotectedinherited

Set the target's preferred loop alignment. Default alignment is zero, it means the target does not care about loop alignment. The alignment is specified in log2(bytes).

Definition at line 1211 of file TargetLowering.h.

1211  {
1213  }
unsigned PrefLoopAlignment
The preferred loop alignment.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setSchedulingPreference ( Sched::Preference  Pref)
inlineprotectedinherited

Specify the target scheduling preference.

Definition at line 983 of file TargetLowering.h.

983  {
984  SchedPreferenceInfo = Pref;
985  }
Sched::Preference SchedPreferenceInfo
void llvm::TargetLoweringBase::setSelectIsExpensive ( bool  isExpensive = true)
inlineprotectedinherited

Tells the code generator not to expand operations into sequences that use the select operations if possible.

Definition at line 1030 of file TargetLowering.h.

1030  {
1031  SelectIsExpensive = isExpensive;
1032  }
void llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore ( unsigned  R)
inlineprotectedinherited

If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

Definition at line 1012 of file TargetLowering.h.

1012  {
1014  }
unsigned StackPointerRegisterToSaveRestore
void llvm::TargetLoweringBase::setSupportJumpTables ( bool  Val)
inlineprotectedinherited

Indicate whether the target can generate code for jump tables.

Definition at line 1000 of file TargetLowering.h.

1000  {
1001  SupportJumpTables = Val;
1002  }
void llvm::TargetLoweringBase::setTargetDAGCombine ( ISD::NodeType  NT)
inlineprotectedinherited

Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method.

Definition at line 1180 of file TargetLowering.h.

1180  {
1181  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1182  TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1183  }
unsigned char TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
void llvm::TargetLoweringBase::setTruncStoreAction ( MVT  ValVT,
MVT  MemVT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified truncating store does not work with the specified type and indicate what to do about it.

Definition at line 1119 of file TargetLowering.h.

1120  {
1121  assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
1122  "Table isn't big enough!");
1123  TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1124  }
uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
assert(Globals.size() > 1)
void llvm::TargetLoweringBase::setUseUnderscoreLongJmp ( bool  Val)
inlineprotectedinherited

Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _. Defaults to false.

Definition at line 995 of file TargetLowering.h.

995  {
996  UseUnderscoreLongJmp = Val;
997  }
void llvm::TargetLoweringBase::setUseUnderscoreSetJmp ( bool  Val)
inlineprotectedinherited

Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _. Defaults to false.

Definition at line 989 of file TargetLowering.h.

989  {
990  UseUnderscoreSetJmp = Val;
991  }
bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm ( const APInt Imm,
Type Ty 
) const
overridevirtual

Returns true if it is beneficial to convert a load of a constant to just the constant itself.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 6324 of file AArch64ISelLowering.cpp.

6325  {
6326  assert(Ty->isIntegerTy());
6327 
6328  unsigned BitSize = Ty->getPrimitiveSizeInBits();
6329  if (BitSize == 0)
6330  return false;
6331 
6332  int64_t Val = Imm.getSExtValue();
6333  if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6334  return true;
6335 
6336  if ((int64_t)Val < 0)
6337  Val = ~Val;
6338  if (BitSize == 32)
6339  Val &= (1LL << 32) - 1;
6340 
6341  unsigned LZ = countLeadingZeros((uint64_t)Val);
6342  unsigned Shift = (63 - LZ) / 16;
6343  // MOVZ is free so return true for one or fewer MOVK.
6344  return (Shift < 3) ? true : false;
6345 }
std::enable_if< std::numeric_limits< T >::is_integer &&!std::numeric_limits< T >::is_signed, std::size_t >::type countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the most significant bit to the least stopping at the first 1...
Definition: MathExtras.h:120
static bool isLogicalImmediate(uint64_t imm, unsigned regSize)
assert(Globals.size() > 1)
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1314
bool isIntegerTy() const
Definition: Type.h:193
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
bool AArch64TargetLowering::shouldExpandAtomicInIR ( Instruction Inst) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 8003 of file AArch64ISelLowering.cpp.

8003  {
8004  // Loads and stores less than 128-bits are already atomic; ones above that
8005  // are doomed anyway, so defer to the default libcall and blame the OS when
8006  // things go wrong:
8007  if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
8008  return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() == 128;
8009  else if (LoadInst *LI = dyn_cast<LoadInst>(Inst))
8010  return LI->getType()->getPrimitiveSizeInBits() == 128;
8011 
8012  // For the real atomic operations, we have ldxr/stxr up to 128 bits.
8013  return Inst->getType()->getPrimitiveSizeInBits() <= 128;
8014 }
LoopInfoBase< BlockT, LoopT > * LI
Definition: LoopInfoImpl.h:412
Type * getType() const
Definition: Value.h:215
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
virtual bool llvm::TargetLoweringBase::shouldExpandBuildVectorWithShuffles ( EVT  ,
unsigned  DefinedValues 
) const
inlinevirtualinherited

Reimplemented in llvm::PPCTargetLowering.

Definition at line 208 of file TargetLowering.h.

209  {
210  return DefinedValues < 3;
211  }
virtual bool llvm::TargetLoweringBase::ShouldShrinkFPConstant ( EVT  ) const
inlinevirtualinherited

If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.

Reimplemented in llvm::X86TargetLowering, llvm::SparcTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 726 of file TargetLowering.h.

726 { return true; }
bool TargetLowering::SimplifyDemandedBits ( SDValue  Op,
const APInt DemandedMask,
APInt KnownZero,
APInt KnownOne,
TargetLoweringOpt TLO,
unsigned  Depth = 0 
) const
inherited

Look at Op. At this point, we know that only the DemandedMask bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the DemandedMask.

SimplifyDemandedBits - Look at Op. At this point, we know that only the DemandedMask bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the DemandedMask.

Definition at line 372 of file TargetLowering.cpp.

377  {
378  unsigned BitWidth = DemandedMask.getBitWidth();
379  assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
380  "Mask size mismatches value type size!");
381  APInt NewMask = DemandedMask;
382  SDLoc dl(Op);
383 
384  // Don't know anything.
385  KnownZero = KnownOne = APInt(BitWidth, 0);
386 
387  // Other users may use these bits.
388  if (!Op.getNode()->hasOneUse()) {
389  if (Depth != 0) {
390  // If not at the root, Just compute the KnownZero/KnownOne bits to
391  // simplify things downstream.
392  TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
393  return false;
394  }
395  // If this is the root being simplified, allow it to have multiple uses,
396  // just set the NewMask to all bits.
397  NewMask = APInt::getAllOnesValue(BitWidth);
398  } else if (DemandedMask == 0) {
399  // Not demanding any bits from Op.
400  if (Op.getOpcode() != ISD::UNDEF)
401  return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
402  return false;
403  } else if (Depth == 6) { // Limit search depth.
404  return false;
405  }
406 
407  APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
408  switch (Op.getOpcode()) {
409  case ISD::Constant:
410  // We know all of the bits for a constant!
411  KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
412  KnownZero = ~KnownOne;
413  return false; // Don't fall through, will infinitely loop.
414  case ISD::AND:
415  // If the RHS is a constant, check to see if the LHS would be zero without
416  // using the bits from the RHS. Below, we use knowledge about the RHS to
417  // simplify the LHS, here we're using information from the LHS to simplify
418  // the RHS.
419  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
420  APInt LHSZero, LHSOne;
421  // Do not increment Depth here; that can cause an infinite loop.
422  TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
423  // If the LHS already has zeros where RHSC does, this and is dead.
424  if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
425  return TLO.CombineTo(Op, Op.getOperand(0));
426  // If any of the set bits in the RHS are known zero on the LHS, shrink
427  // the constant.
428  if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
429  return true;
430  }
431 
432  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
433  KnownOne, TLO, Depth+1))
434  return true;
435  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
436  if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
437  KnownZero2, KnownOne2, TLO, Depth+1))
438  return true;
439  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
440 
441  // If all of the demanded bits are known one on one side, return the other.
442  // These bits cannot contribute to the result of the 'and'.
443  if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
444  return TLO.CombineTo(Op, Op.getOperand(0));
445  if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
446  return TLO.CombineTo(Op, Op.getOperand(1));
447  // If all of the demanded bits in the inputs are known zeros, return zero.
448  if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
449  return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
450  // If the RHS is a constant, see if we can simplify it.
451  if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
452  return true;
453  // If the operation can be done in a smaller type, do so.
454  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
455  return true;
456 
457  // Output known-1 bits are only known if set in both the LHS & RHS.
458  KnownOne &= KnownOne2;
459  // Output known-0 are known to be clear if zero in either the LHS | RHS.
460  KnownZero |= KnownZero2;
461  break;
462  case ISD::OR:
463  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
464  KnownOne, TLO, Depth+1))
465  return true;
466  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
467  if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
468  KnownZero2, KnownOne2, TLO, Depth+1))
469  return true;
470  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
471 
472  // If all of the demanded bits are known zero on one side, return the other.
473  // These bits cannot contribute to the result of the 'or'.
474  if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
475  return TLO.CombineTo(Op, Op.getOperand(0));
476  if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
477  return TLO.CombineTo(Op, Op.getOperand(1));
478  // If all of the potentially set bits on one side are known to be set on
479  // the other side, just use the 'other' side.
480  if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
481  return TLO.CombineTo(Op, Op.getOperand(0));
482  if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
483  return TLO.CombineTo(Op, Op.getOperand(1));
484  // If the RHS is a constant, see if we can simplify it.
485  if (TLO.ShrinkDemandedConstant(Op, NewMask))
486  return true;
487  // If the operation can be done in a smaller type, do so.
488  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
489  return true;
490 
491  // Output known-0 bits are only known if clear in both the LHS & RHS.
492  KnownZero &= KnownZero2;
493  // Output known-1 are known to be set if set in either the LHS | RHS.
494  KnownOne |= KnownOne2;
495  break;
496  case ISD::XOR:
497  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
498  KnownOne, TLO, Depth+1))
499  return true;
500  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
501  if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
502  KnownOne2, TLO, Depth+1))
503  return true;
504  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
505 
506  // If all of the demanded bits are known zero on one side, return the other.
507  // These bits cannot contribute to the result of the 'xor'.
508  if ((KnownZero & NewMask) == NewMask)
509  return TLO.CombineTo(Op, Op.getOperand(0));
510  if ((KnownZero2 & NewMask) == NewMask)
511  return TLO.CombineTo(Op, Op.getOperand(1));
512  // If the operation can be done in a smaller type, do so.
513  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
514  return true;
515 
516  // If all of the unknown bits are known to be zero on one side or the other
517  // (but not both) turn this into an *inclusive* or.
518  // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
519  if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
520  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
521  Op.getOperand(0),
522  Op.getOperand(1)));
523 
524  // Output known-0 bits are known if clear or set in both the LHS & RHS.
525  KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
526  // Output known-1 are known to be set if set in only one of the LHS, RHS.
527  KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
528 
529  // If all of the demanded bits on one side are known, and all of the set
530  // bits on that side are also known to be set on the other side, turn this
531  // into an AND, as we know the bits will be cleared.
532  // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
533  // NB: it is okay if more bits are known than are requested
534  if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
535  if (KnownOne == KnownOne2) { // set bits are the same on both sides
536  EVT VT = Op.getValueType();
537  SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
538  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
539  Op.getOperand(0), ANDC));
540  }
541  }
542 
543  // If the RHS is a constant, see if we can simplify it.
544  // for XOR, we prefer to force bits to 1 if they will make a -1.
545  // if we can't force bits, try to shrink constant
546  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
547  APInt Expanded = C->getAPIntValue() | (~NewMask);
548  // if we can expand it to have all bits set, do it
549  if (Expanded.isAllOnesValue()) {
550  if (Expanded != C->getAPIntValue()) {
551  EVT VT = Op.getValueType();
552  SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
553  TLO.DAG.getConstant(Expanded, VT));
554  return TLO.CombineTo(Op, New);
555  }
556  // if it already has all the bits set, nothing to change
557  // but don't shrink either!
558  } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
559  return true;
560  }
561  }
562 
563  KnownZero = KnownZeroOut;
564  KnownOne = KnownOneOut;
565  break;
566  case ISD::SELECT:
567  if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
568  KnownOne, TLO, Depth+1))
569  return true;
570  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
571  KnownOne2, TLO, Depth+1))
572  return true;
573  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
574  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
575 
576  // If the operands are constants, see if we can simplify them.
577  if (TLO.ShrinkDemandedConstant(Op, NewMask))
578  return true;
579 
580  // Only known if known in both the LHS and RHS.
581  KnownOne &= KnownOne2;
582  KnownZero &= KnownZero2;
583  break;
584  case ISD::SELECT_CC:
585  if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
586  KnownOne, TLO, Depth+1))
587  return true;
588  if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
589  KnownOne2, TLO, Depth+1))
590  return true;
591  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
592  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
593 
594  // If the operands are constants, see if we can simplify them.
595  if (TLO.ShrinkDemandedConstant(Op, NewMask))
596  return true;
597 
598  // Only known if known in both the LHS and RHS.
599  KnownOne &= KnownOne2;
600  KnownZero &= KnownZero2;
601  break;
602  case ISD::SHL:
603  if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
604  unsigned ShAmt = SA->getZExtValue();
605  SDValue InOp = Op.getOperand(0);
606 
607  // If the shift count is an invalid immediate, don't do anything.
608  if (ShAmt >= BitWidth)
609  break;
610 
611  // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
612  // single shift. We can do this if the bottom bits (which are shifted
613  // out) are never demanded.
614  if (InOp.getOpcode() == ISD::SRL &&
615  isa<ConstantSDNode>(InOp.getOperand(1))) {
616  if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
617  unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
618  unsigned Opc = ISD::SHL;
619  int Diff = ShAmt-C1;
620  if (Diff < 0) {
621  Diff = -Diff;
622  Opc = ISD::SRL;
623  }
624 
625  SDValue NewSA =
626  TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
627  EVT VT = Op.getValueType();
628  return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
629  InOp.getOperand(0), NewSA));
630  }
631  }
632 
633  if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
634  KnownZero, KnownOne, TLO, Depth+1))
635  return true;
636 
637  // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
638  // are not demanded. This will likely allow the anyext to be folded away.
639  if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
640  SDValue InnerOp = InOp.getNode()->getOperand(0);
641  EVT InnerVT = InnerOp.getValueType();
642  unsigned InnerBits = InnerVT.getSizeInBits();
643  if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
644  isTypeDesirableForOp(ISD::SHL, InnerVT)) {
645  EVT ShTy = getShiftAmountTy(InnerVT);
646  if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
647  ShTy = InnerVT;
648  SDValue NarrowShl =
649  TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
650  TLO.DAG.getConstant(ShAmt, ShTy));
651  return
652  TLO.CombineTo(Op,
653  TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
654  NarrowShl));
655  }
656  // Repeat the SHL optimization above in cases where an extension
657  // intervenes: (shl (anyext (shr x, c1)), c2) to
658  // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
659  // aren't demanded (as above) and that the shifted upper c1 bits of
660  // x aren't demanded.
661  if (InOp.hasOneUse() &&
662  InnerOp.getOpcode() == ISD::SRL &&
663  InnerOp.hasOneUse() &&
664  isa<ConstantSDNode>(InnerOp.getOperand(1))) {
665  uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
666  ->getZExtValue();
667  if (InnerShAmt < ShAmt &&
668  InnerShAmt < InnerBits &&
669  NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
670  NewMask.trunc(ShAmt) == 0) {
671  SDValue NewSA =
672  TLO.DAG.getConstant(ShAmt - InnerShAmt,
673  Op.getOperand(1).getValueType());
674  EVT VT = Op.getValueType();
675  SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
676  InnerOp.getOperand(0));
677  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
678  NewExt, NewSA));
679  }
680  }
681  }
682 
683  KnownZero <<= SA->getZExtValue();
684  KnownOne <<= SA->getZExtValue();
685  // low bits known zero.
686  KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
687  }
688  break;
689  case ISD::SRL:
690  if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
691  EVT VT = Op.getValueType();
692  unsigned ShAmt = SA->getZExtValue();
693  unsigned VTSize = VT.getSizeInBits();
694  SDValue InOp = Op.getOperand(0);
695 
696  // If the shift count is an invalid immediate, don't do anything.
697  if (ShAmt >= BitWidth)
698  break;
699 
700  // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
701  // single shift. We can do this if the top bits (which are shifted out)
702  // are never demanded.
703  if (InOp.getOpcode() == ISD::SHL &&
704  isa<ConstantSDNode>(InOp.getOperand(1))) {
705  if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
706  unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
707  unsigned Opc = ISD::SRL;
708  int Diff = ShAmt-C1;
709  if (Diff < 0) {
710  Diff = -Diff;
711  Opc = ISD::SHL;
712  }
713 
714  SDValue NewSA =
715  TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
716  return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
717  InOp.getOperand(0), NewSA));
718  }
719  }
720 
721  // Compute the new bits that are at the top now.
722  if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
723  KnownZero, KnownOne, TLO, Depth+1))
724  return true;
725  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
726  KnownZero = KnownZero.lshr(ShAmt);
727  KnownOne = KnownOne.lshr(ShAmt);
728 
729  APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
730  KnownZero |= HighBits; // High bits known zero.
731  }
732  break;
733  case ISD::SRA:
734  // If this is an arithmetic shift right and only the low-bit is set, we can
735  // always convert this into a logical shr, even if the shift amount is
736  // variable. The low bit of the shift cannot be an input sign bit unless
737  // the shift amount is >= the size of the datatype, which is undefined.
738  if (NewMask == 1)
739  return TLO.CombineTo(Op,
740  TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
741  Op.getOperand(0), Op.getOperand(1)));
742 
743  if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
744  EVT VT = Op.getValueType();
745  unsigned ShAmt = SA->getZExtValue();
746 
747  // If the shift count is an invalid immediate, don't do anything.
748  if (ShAmt >= BitWidth)
749  break;
750 
751  APInt InDemandedMask = (NewMask << ShAmt);
752 
753  // If any of the demanded bits are produced by the sign extension, we also
754  // demand the input sign bit.
755  APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
756  if (HighBits.intersects(NewMask))
757  InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
758 
759  if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
760  KnownZero, KnownOne, TLO, Depth+1))
761  return true;
762  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
763  KnownZero = KnownZero.lshr(ShAmt);
764  KnownOne = KnownOne.lshr(ShAmt);
765 
766  // Handle the sign bit, adjusted to where it is now in the mask.
767  APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
768 
769  // If the input sign bit is known to be zero, or if none of the top bits
770  // are demanded, turn this into an unsigned shift right.
771  if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits)
772  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
773  Op.getOperand(0),
774  Op.getOperand(1)));
775 
776  int Log2 = NewMask.exactLogBase2();
777  if (Log2 >= 0) {
778  // The bit must come from the sign.
779  SDValue NewSA =
780  TLO.DAG.getConstant(BitWidth - 1 - Log2,
781  Op.getOperand(1).getValueType());
782  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
783  Op.getOperand(0), NewSA));
784  }
785 
786  if (KnownOne.intersects(SignBit))
787  // New bits are known one.
788  KnownOne |= HighBits;
789  }
790  break;
791  case ISD::SIGN_EXTEND_INREG: {
792  EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
793 
794  APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
795  // If we only care about the highest bit, don't bother shifting right.
796  if (MsbMask == DemandedMask) {
797  unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
798  SDValue InOp = Op.getOperand(0);
799 
800  // Compute the correct shift amount type, which must be getShiftAmountTy
801  // for scalar types after legalization.
802  EVT ShiftAmtTy = Op.getValueType();
803  if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
804  ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
805 
806  SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
807  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
808  Op.getValueType(), InOp, ShiftAmt));
809  }
810 
811  // Sign extension. Compute the demanded bits in the result that are not
812  // present in the input.
813  APInt NewBits =
814  APInt::getHighBitsSet(BitWidth,
815  BitWidth - ExVT.getScalarType().getSizeInBits());
816 
817  // If none of the extended bits are demanded, eliminate the sextinreg.
818  if ((NewBits & NewMask) == 0)
819  return TLO.CombineTo(Op, Op.getOperand(0));
820 
821  APInt InSignBit =
822  APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
823  APInt InputDemandedBits =
824  APInt::getLowBitsSet(BitWidth,
825  ExVT.getScalarType().getSizeInBits()) &
826  NewMask;
827 
828  // Since the sign extended bits are demanded, we know that the sign
829  // bit is demanded.
830  InputDemandedBits |= InSignBit;
831 
832  if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
833  KnownZero, KnownOne, TLO, Depth+1))
834  return true;
835  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
836 
837  // If the sign bit of the input is known set or clear, then we know the
838  // top bits of the result.
839 
840  // If the input sign bit is known zero, convert this into a zero extension.
841  if (KnownZero.intersects(InSignBit))
842  return TLO.CombineTo(Op,
843  TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
844 
845  if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
846  KnownOne |= NewBits;
847  KnownZero &= ~NewBits;
848  } else { // Input sign bit unknown
849  KnownZero &= ~NewBits;
850  KnownOne &= ~NewBits;
851  }
852  break;
853  }
854  case ISD::BUILD_PAIR: {
855  EVT HalfVT = Op.getOperand(0).getValueType();
856  unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
857 
858  APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
859  APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
860 
861  APInt KnownZeroLo, KnownOneLo;
862  APInt KnownZeroHi, KnownOneHi;
863 
864  if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo,
865  KnownOneLo, TLO, Depth + 1))
866  return true;
867 
868  if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi,
869  KnownOneHi, TLO, Depth + 1))
870  return true;
871 
872  KnownZero = KnownZeroLo.zext(BitWidth) |
873  KnownZeroHi.zext(BitWidth).shl(HalfBitWidth);
874 
875  KnownOne = KnownOneLo.zext(BitWidth) |
876  KnownOneHi.zext(BitWidth).shl(HalfBitWidth);
877  break;
878  }
879  case ISD::ZERO_EXTEND: {
880  unsigned OperandBitWidth =
882  APInt InMask = NewMask.trunc(OperandBitWidth);
883 
884  // If none of the top bits are demanded, convert this into an any_extend.
885  APInt NewBits =
886  APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
887  if (!NewBits.intersects(NewMask))
888  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
889  Op.getValueType(),
890  Op.getOperand(0)));
891 
892  if (SimplifyDemandedBits(Op.getOperand(0), InMask,
893  KnownZero, KnownOne, TLO, Depth+1))
894  return true;
895  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
896  KnownZero = KnownZero.zext(BitWidth);
897  KnownOne = KnownOne.zext(BitWidth);
898  KnownZero |= NewBits;
899  break;
900  }
901  case ISD::SIGN_EXTEND: {
902  EVT InVT = Op.getOperand(0).getValueType();
903  unsigned InBits = InVT.getScalarType().getSizeInBits();
904  APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
905  APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
906  APInt NewBits = ~InMask & NewMask;
907 
908  // If none of the top bits are demanded, convert this into an any_extend.
909  if (NewBits == 0)
910  return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
911  Op.getValueType(),
912  Op.getOperand(0)));
913 
914  // Since some of the sign extended bits are demanded, we know that the sign
915  // bit is demanded.
916  APInt InDemandedBits = InMask & NewMask;
917  InDemandedBits |= InSignBit;
918  InDemandedBits = InDemandedBits.trunc(InBits);
919 
920  if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
921  KnownOne, TLO, Depth+1))
922  return true;
923  KnownZero = KnownZero.zext(BitWidth);
924  KnownOne = KnownOne.zext(BitWidth);
925 
926  // If the sign bit is known zero, convert this to a zero extend.
927  if (KnownZero.intersects(InSignBit))
928  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
929  Op.getValueType(),
930  Op.getOperand(0)));
931 
932  // If the sign bit is known one, the top bits match.
933  if (KnownOne.intersects(InSignBit)) {
934  KnownOne |= NewBits;
935  assert((KnownZero & NewBits) == 0);
936  } else { // Otherwise, top bits aren't known.
937  assert((KnownOne & NewBits) == 0);
938  assert((KnownZero & NewBits) == 0);
939  }
940  break;
941  }
942  case ISD::ANY_EXTEND: {
943  unsigned OperandBitWidth =
945  APInt InMask = NewMask.trunc(OperandBitWidth);
946  if (SimplifyDemandedBits(Op.getOperand(0), InMask,
947  KnownZero, KnownOne, TLO, Depth+1))
948  return true;
949  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
950  KnownZero = KnownZero.zext(BitWidth);
951  KnownOne = KnownOne.zext(BitWidth);
952  break;
953  }
954  case ISD::TRUNCATE: {
955  // Simplify the input, using demanded bit information, and compute the known
956  // zero/one bits live out.
957  unsigned OperandBitWidth =
959  APInt TruncMask = NewMask.zext(OperandBitWidth);
960  if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
961  KnownZero, KnownOne, TLO, Depth+1))
962  return true;
963  KnownZero = KnownZero.trunc(BitWidth);
964  KnownOne = KnownOne.trunc(BitWidth);
965 
966  // If the input is only used by this truncate, see if we can shrink it based
967  // on the known demanded bits.
968  if (Op.getOperand(0).getNode()->hasOneUse()) {
969  SDValue In = Op.getOperand(0);
970  switch (In.getOpcode()) {
971  default: break;
972  case ISD::SRL:
973  // Shrink SRL by a constant if none of the high bits shifted in are
974  // demanded.
975  if (TLO.LegalTypes() &&
977  // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
978  // undesirable.
979  break;
981  if (!ShAmt)
982  break;
983  SDValue Shift = In.getOperand(1);
984  if (TLO.LegalTypes()) {
985  uint64_t ShVal = ShAmt->getZExtValue();
986  Shift =
987  TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
988  }
989 
990  APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
991  OperandBitWidth - BitWidth);
992  HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
993 
994  if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
995  // None of the shifted in bits are needed. Add a truncate of the
996  // shift input, then shift it.
997  SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
998  Op.getValueType(),
999  In.getOperand(0));
1000  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1001  Op.getValueType(),
1002  NewTrunc,
1003  Shift));
1004  }
1005  break;
1006  }
1007  }
1008 
1009  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1010  break;
1011  }
1012  case ISD::AssertZext: {
1013  // AssertZext demands all of the high bits, plus any of the low bits
1014  // demanded by its users.
1015  EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1016  APInt InMask = APInt::getLowBitsSet(BitWidth,
1017  VT.getSizeInBits());
1018  if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1019  KnownZero, KnownOne, TLO, Depth+1))
1020  return true;
1021  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1022 
1023  KnownZero |= ~InMask & NewMask;
1024  break;
1025  }
1026  case ISD::BITCAST:
1027  // If this is an FP->Int bitcast and if the sign bit is the only
1028  // thing demanded, turn this into a FGETSIGN.
1029  if (!TLO.LegalOperations() &&
1030  !Op.getValueType().isVector() &&
1031  !Op.getOperand(0).getValueType().isVector() &&
1032  NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1034  bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1036  if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1037  EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1038  // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1039  // place. We expect the SHL to be eliminated by other optimizations.
1040  SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1041  unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1042  if (!OpVTLegal && OpVTSizeInBits > 32)
1043  Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1044  unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1045  SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1046  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1047  Op.getValueType(),
1048  Sign, ShAmt));
1049  }
1050  }
1051  break;
1052  case ISD::ADD:
1053  case ISD::MUL:
1054  case ISD::SUB: {
1055  // Add, Sub, and Mul don't demand any bits in positions beyond that
1056  // of the highest bit demanded of them.
1057  APInt LoMask = APInt::getLowBitsSet(BitWidth,
1058  BitWidth - NewMask.countLeadingZeros());
1059  if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1060  KnownOne2, TLO, Depth+1))
1061  return true;
1062  if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1063  KnownOne2, TLO, Depth+1))
1064  return true;
1065  // See if the operation should be performed at a smaller bit width.
1066  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1067  return true;
1068  }
1069  // FALL THROUGH
1070  default:
1071  // Just use computeKnownBits to compute output bits.
1072  TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
1073  break;
1074  }
1075 
1076  // If we know the value of all of the demanded bits, return this as a
1077  // constant.
1078  if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1079  return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1080 
1081  return false;
1082 }
static APInt getSignBit(unsigned BitWidth)
Get the SignBit for a specific bit width.
Definition: APInt.h:441
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:448
bool hasOneUse() const
bool hasOneUse() const
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:526
unsigned getOpcode() const
const SDValue & getOperand(unsigned Num) const
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const
double trunc(double x);
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
EVT getShiftAmountTy(EVT LHSTy) const
APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.cpp:1128
EVT getScalarType() const
Definition: ValueTypes.h:211
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
APInt LLVM_ATTRIBUTE_UNUSED_RESULT shl(unsigned shiftAmt) const
Left-shift function.
Definition: APInt.h:852
UNDEF - An undefined node.
Definition: ISDOpcodes.h:159
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:240
assert(Globals.size() > 1)
bool intersects(const APInt &RHS) const
Definition: APInt.h:1140
APInt LLVM_ATTRIBUTE_UNUSED_RESULT trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:920
const SDValue & getOperand(unsigned i) const
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
APInt getLoBits(unsigned numBits) const
Compute an APInt containing numBits lowbits from this APInt.
Definition: APInt.cpp:677
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1248
unsigned getOpcode() const
bool isIntN(unsigned N, int64_t x)
Definition: MathExtras.h:330
APInt getHiBits(unsigned numBits) const
Compute an APInt containing numBits highbits from this APInt.
Definition: APInt.cpp:672
int32_t exactLogBase2() const
Definition: APInt.h:1534
Class for arbitrary precision integers.
Definition: APInt.h:75
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
Definition: APInt.h:493
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:338
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
bool isSimple() const
Definition: ValueTypes.h:95
APInt LLVM_ATTRIBUTE_UNUSED_RESULT zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:984
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
uint64_t getZExtValue() const
SDValue TargetLowering::SimplifySetCC ( EVT  VT,
SDValue  N0,
SDValue  N1,
ISD::CondCode  Cond,
bool  foldBooleans,
DAGCombinerInfo DCI,
SDLoc  dl 
) const
inherited

Try to simplify a setcc built with the specified operands and cc. If it is unable to simplify it, return a null SDValue.

SimplifySetCC - Try to simplify a setcc built with the specified operands and cc. If it is unable to simplify it, return a null SDValue.

Definition at line 1206 of file TargetLowering.cpp.

1208  {
1209  SelectionDAG &DAG = DCI.DAG;
1210 
1211  // These setcc operations always fold.
1212  switch (Cond) {
1213  default: break;
1214  case ISD::SETFALSE:
1215  case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1216  case ISD::SETTRUE:
1217  case ISD::SETTRUE2: {
1220  return DAG.getConstant(
1221  Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT);
1222  }
1223  }
1224 
1225  // Ensure that the constant occurs on the RHS, and fold constant
1226  // comparisons.
1227  ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1228  if (isa<ConstantSDNode>(N0.getNode()) &&
1229  (DCI.isBeforeLegalizeOps() ||
1230  isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1231  return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1232 
1233  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1234  const APInt &C1 = N1C->getAPIntValue();
1235 
1236  // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1237  // equality comparison, then we're just comparing whether X itself is
1238  // zero.
1239  if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1240  N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1241  N0.getOperand(1).getOpcode() == ISD::Constant) {
1242  const APInt &ShAmt
1243  = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1244  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1245  ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1246  if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1247  // (srl (ctlz x), 5) == 0 -> X != 0
1248  // (srl (ctlz x), 5) != 1 -> X != 0
1249  Cond = ISD::SETNE;
1250  } else {
1251  // (srl (ctlz x), 5) != 0 -> X == 0
1252  // (srl (ctlz x), 5) == 1 -> X == 0
1253  Cond = ISD::SETEQ;
1254  }
1255  SDValue Zero = DAG.getConstant(0, N0.getValueType());
1256  return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1257  Zero, Cond);
1258  }
1259  }
1260 
1261  SDValue CTPOP = N0;
1262  // Look through truncs that don't change the value of a ctpop.
1263  if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1264  CTPOP = N0.getOperand(0);
1265 
1266  if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1267  (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1268  Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1269  EVT CTVT = CTPOP.getValueType();
1270  SDValue CTOp = CTPOP.getOperand(0);
1271 
1272  // (ctpop x) u< 2 -> (x & x-1) == 0
1273  // (ctpop x) u> 1 -> (x & x-1) != 0
1274  if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1275  SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1276  DAG.getConstant(1, CTVT));
1277  SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1279  return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1280  }
1281 
1282  // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1283  }
1284 
1285  // (zext x) == C --> x == (trunc C)
1286  if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1287  (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1288  unsigned MinBits = N0.getValueSizeInBits();
1289  SDValue PreZExt;
1290  if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1291  // ZExt
1292  MinBits = N0->getOperand(0).getValueSizeInBits();
1293  PreZExt = N0->getOperand(0);
1294  } else if (N0->getOpcode() == ISD::AND) {
1295  // DAGCombine turns costly ZExts into ANDs
1296  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1297  if ((C->getAPIntValue()+1).isPowerOf2()) {
1298  MinBits = C->getAPIntValue().countTrailingOnes();
1299  PreZExt = N0->getOperand(0);
1300  }
1301  } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1302  // ZEXTLOAD
1303  if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1304  MinBits = LN0->getMemoryVT().getSizeInBits();
1305  PreZExt = N0;
1306  }
1307  }
1308 
1309  // Make sure we're not losing bits from the constant.
1310  if (MinBits > 0 &&
1311  MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) {
1312  EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1313  if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1314  // Will get folded away.
1315  SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
1316  SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
1317  return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1318  }
1319  }
1320  }
1321 
1322  // If the LHS is '(and load, const)', the RHS is 0,
1323  // the test is for equality or unsigned, and all 1 bits of the const are
1324  // in the same partial word, see if we can shorten the load.
1325  if (DCI.isBeforeLegalize() &&
1326  !ISD::isSignedIntSetCC(Cond) &&
1327  N0.getOpcode() == ISD::AND && C1 == 0 &&
1328  N0.getNode()->hasOneUse() &&
1329  isa<LoadSDNode>(N0.getOperand(0)) &&
1330  N0.getOperand(0).getNode()->hasOneUse() &&
1331  isa<ConstantSDNode>(N0.getOperand(1))) {
1332  LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1333  APInt bestMask;
1334  unsigned bestWidth = 0, bestOffset = 0;
1335  if (!Lod->isVolatile() && Lod->isUnindexed()) {
1336  unsigned origWidth = N0.getValueType().getSizeInBits();
1337  unsigned maskWidth = origWidth;
1338  // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1339  // 8 bits, but have to be careful...
1340  if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1341  origWidth = Lod->getMemoryVT().getSizeInBits();
1342  const APInt &Mask =
1343  cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1344  for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1345  APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1346  for (unsigned offset=0; offset<origWidth/width; offset++) {
1347  if ((newMask & Mask) == Mask) {
1348  if (!getDataLayout()->isLittleEndian())
1349  bestOffset = (origWidth/width - offset - 1) * (width/8);
1350  else
1351  bestOffset = (uint64_t)offset * (width/8);
1352  bestMask = Mask.lshr(offset * (width/8) * 8);
1353  bestWidth = width;
1354  break;
1355  }
1356  newMask = newMask << width;
1357  }
1358  }
1359  }
1360  if (bestWidth) {
1361  EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1362  if (newVT.isRound()) {
1363  EVT PtrType = Lod->getOperand(1).getValueType();
1364  SDValue Ptr = Lod->getBasePtr();
1365  if (bestOffset != 0)
1366  Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1367  DAG.getConstant(bestOffset, PtrType));
1368  unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1369  SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1370  Lod->getPointerInfo().getWithOffset(bestOffset),
1371  false, false, false, NewAlign);
1372  return DAG.getSetCC(dl, VT,
1373  DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1374  DAG.getConstant(bestMask.trunc(bestWidth),
1375  newVT)),
1376  DAG.getConstant(0LL, newVT), Cond);
1377  }
1378  }
1379  }
1380 
1381  // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1382  if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1383  unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1384 
1385  // If the comparison constant has bits in the upper part, the
1386  // zero-extended value could never match.
1387  if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1388  C1.getBitWidth() - InSize))) {
1389  switch (Cond) {
1390  case ISD::SETUGT:
1391  case ISD::SETUGE:
1392  case ISD::SETEQ: return DAG.getConstant(0, VT);
1393  case ISD::SETULT:
1394  case ISD::SETULE:
1395  case ISD::SETNE: return DAG.getConstant(1, VT);
1396  case ISD::SETGT:
1397  case ISD::SETGE:
1398  // True if the sign bit of C1 is set.
1399  return DAG.getConstant(C1.isNegative(), VT);
1400  case ISD::SETLT:
1401  case ISD::SETLE:
1402  // True if the sign bit of C1 isn't set.
1403  return DAG.getConstant(C1.isNonNegative(), VT);
1404  default:
1405  break;
1406  }
1407  }
1408 
1409  // Otherwise, we can perform the comparison with the low bits.
1410  switch (Cond) {
1411  case ISD::SETEQ:
1412  case ISD::SETNE:
1413  case ISD::SETUGT:
1414  case ISD::SETUGE:
1415  case ISD::SETULT:
1416  case ISD::SETULE: {
1417  EVT newVT = N0.getOperand(0).getValueType();
1418  if (DCI.isBeforeLegalizeOps() ||
1419  (isOperationLegal(ISD::SETCC, newVT) &&
1420  getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
1421  EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT);
1422  SDValue NewConst = DAG.getConstant(C1.trunc(InSize), newVT);
1423 
1424  SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
1425  NewConst, Cond);
1426  return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
1427  }
1428  break;
1429  }
1430  default:
1431  break; // todo, be more careful with signed comparisons
1432  }
1433  } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1434  (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1435  EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1436  unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1437  EVT ExtDstTy = N0.getValueType();
1438  unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1439 
1440  // If the constant doesn't fit into the number of bits for the source of
1441  // the sign extension, it is impossible for both sides to be equal.
1442  if (C1.getMinSignedBits() > ExtSrcTyBits)
1443  return DAG.getConstant(Cond == ISD::SETNE, VT);
1444 
1445  SDValue ZextOp;
1446  EVT Op0Ty = N0.getOperand(0).getValueType();
1447  if (Op0Ty == ExtSrcTy) {
1448  ZextOp = N0.getOperand(0);
1449  } else {
1450  APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1451  ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1452  DAG.getConstant(Imm, Op0Ty));
1453  }
1454  if (!DCI.isCalledByLegalizer())
1455  DCI.AddToWorklist(ZextOp.getNode());
1456  // Otherwise, make this a use of a zext.
1457  return DAG.getSetCC(dl, VT, ZextOp,
1459  ExtDstTyBits,
1460  ExtSrcTyBits),
1461  ExtDstTy),
1462  Cond);
1463  } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1464  (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1465  // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1466  if (N0.getOpcode() == ISD::SETCC &&
1467  isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1468  bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1469  if (TrueWhenTrue)
1470  return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1471  // Invert the condition.
1472  ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1473  CC = ISD::getSetCCInverse(CC,
1474  N0.getOperand(0).getValueType().isInteger());
1475  if (DCI.isBeforeLegalizeOps() ||
1476  isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
1477  return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1478  }
1479 
1480  if ((N0.getOpcode() == ISD::XOR ||
1481  (N0.getOpcode() == ISD::AND &&
1482  N0.getOperand(0).getOpcode() == ISD::XOR &&
1483  N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1484  isa<ConstantSDNode>(N0.getOperand(1)) &&
1485  cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1486  // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1487  // can only do this if the top bits are known zero.
1488  unsigned BitWidth = N0.getValueSizeInBits();
1489  if (DAG.MaskedValueIsZero(N0,
1490  APInt::getHighBitsSet(BitWidth,
1491  BitWidth-1))) {
1492  // Okay, get the un-inverted input value.
1493  SDValue Val;
1494  if (N0.getOpcode() == ISD::XOR)
1495  Val = N0.getOperand(0);
1496  else {
1497  assert(N0.getOpcode() == ISD::AND &&
1498  N0.getOperand(0).getOpcode() == ISD::XOR);
1499  // ((X^1)&1)^1 -> X & 1
1500  Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1501  N0.getOperand(0).getOperand(0),
1502  N0.getOperand(1));
1503  }
1504 
1505  return DAG.getSetCC(dl, VT, Val, N1,
1506  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1507  }
1508  } else if (N1C->getAPIntValue() == 1 &&
1509  (VT == MVT::i1 ||
1510  getBooleanContents(N0->getValueType(0)) ==
1512  SDValue Op0 = N0;
1513  if (Op0.getOpcode() == ISD::TRUNCATE)
1514  Op0 = Op0.getOperand(0);
1515 
1516  if ((Op0.getOpcode() == ISD::XOR) &&
1517  Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1518  Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1519  // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1520  Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1521  return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1522  Cond);
1523  }
1524  if (Op0.getOpcode() == ISD::AND &&
1525  isa<ConstantSDNode>(Op0.getOperand(1)) &&
1526  cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1527  // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1528  if (Op0.getValueType().bitsGT(VT))
1529  Op0 = DAG.getNode(ISD::AND, dl, VT,
1530  DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1531  DAG.getConstant(1, VT));
1532  else if (Op0.getValueType().bitsLT(VT))
1533  Op0 = DAG.getNode(ISD::AND, dl, VT,
1534  DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1535  DAG.getConstant(1, VT));
1536 
1537  return DAG.getSetCC(dl, VT, Op0,
1538  DAG.getConstant(0, Op0.getValueType()),
1539  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1540  }
1541  if (Op0.getOpcode() == ISD::AssertZext &&
1542  cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1543  return DAG.getSetCC(dl, VT, Op0,
1544  DAG.getConstant(0, Op0.getValueType()),
1545  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1546  }
1547  }
1548 
1549  APInt MinVal, MaxVal;
1550  unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1551  if (ISD::isSignedIntSetCC(Cond)) {
1552  MinVal = APInt::getSignedMinValue(OperandBitSize);
1553  MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1554  } else {
1555  MinVal = APInt::getMinValue(OperandBitSize);
1556  MaxVal = APInt::getMaxValue(OperandBitSize);
1557  }
1558 
1559  // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1560  if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1561  if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1562  // X >= C0 --> X > (C0 - 1)
1563  APInt C = C1 - 1;
1564  ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
1565  if ((DCI.isBeforeLegalizeOps() ||
1566  isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1567  (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1569  return DAG.getSetCC(dl, VT, N0,
1570  DAG.getConstant(C, N1.getValueType()),
1571  NewCC);
1572  }
1573  }
1574 
1575  if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1576  if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1577  // X <= C0 --> X < (C0 + 1)
1578  APInt C = C1 + 1;
1579  ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
1580  if ((DCI.isBeforeLegalizeOps() ||
1581  isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1582  (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1584  return DAG.getSetCC(dl, VT, N0,
1585  DAG.getConstant(C, N1.getValueType()),
1586  NewCC);
1587  }
1588  }
1589 
1590  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1591  return DAG.getConstant(0, VT); // X < MIN --> false
1592  if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1593  return DAG.getConstant(1, VT); // X >= MIN --> true
1594  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1595  return DAG.getConstant(0, VT); // X > MAX --> false
1596  if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1597  return DAG.getConstant(1, VT); // X <= MAX --> true
1598 
1599  // Canonicalize setgt X, Min --> setne X, Min
1600  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1601  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1602  // Canonicalize setlt X, Max --> setne X, Max
1603  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1604  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1605 
1606  // If we have setult X, 1, turn it into seteq X, 0
1607  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1608  return DAG.getSetCC(dl, VT, N0,
1609  DAG.getConstant(MinVal, N0.getValueType()),
1610  ISD::SETEQ);
1611  // If we have setugt X, Max-1, turn it into seteq X, Max
1612  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1613  return DAG.getSetCC(dl, VT, N0,
1614  DAG.getConstant(MaxVal, N0.getValueType()),
1615  ISD::SETEQ);
1616 
1617  // If we have "setcc X, C0", check to see if we can shrink the immediate
1618  // by changing cc.
1619 
1620  // SETUGT X, SINTMAX -> SETLT X, 0
1621  if (Cond == ISD::SETUGT &&
1622  C1 == APInt::getSignedMaxValue(OperandBitSize))
1623  return DAG.getSetCC(dl, VT, N0,
1624  DAG.getConstant(0, N1.getValueType()),
1625  ISD::SETLT);
1626 
1627  // SETULT X, SINTMIN -> SETGT X, -1
1628  if (Cond == ISD::SETULT &&
1629  C1 == APInt::getSignedMinValue(OperandBitSize)) {
1630  SDValue ConstMinusOne =
1631  DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1632  N1.getValueType());
1633  return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1634  }
1635 
1636  // Fold bit comparisons when we can.
1637  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1638  (VT == N0.getValueType() ||
1639  (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1640  N0.getOpcode() == ISD::AND)
1641  if (ConstantSDNode *AndRHS =
1642  dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1643  EVT ShiftTy = DCI.isBeforeLegalize() ?
1645  if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1646  // Perform the xform if the AND RHS is a single bit.
1647  if (AndRHS->getAPIntValue().isPowerOf2()) {
1648  return DAG.getNode(ISD::TRUNCATE, dl, VT,
1649  DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1650  DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
1651  }
1652  } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1653  // (X & 8) == 8 --> (X & 8) >> 3
1654  // Perform the xform if C1 is a single bit.
1655  if (C1.isPowerOf2()) {
1656  return DAG.getNode(ISD::TRUNCATE, dl, VT,
1657  DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1658  DAG.getConstant(C1.logBase2(), ShiftTy)));
1659  }
1660  }
1661  }
1662 
1663  if (C1.getMinSignedBits() <= 64 &&
1664  !isLegalICmpImmediate(C1.getSExtValue())) {
1665  // (X & -256) == 256 -> (X >> 8) == 1
1666  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1667  N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1668  if (ConstantSDNode *AndRHS =
1669  dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1670  const APInt &AndRHSC = AndRHS->getAPIntValue();
1671  if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1672  unsigned ShiftBits = AndRHSC.countTrailingZeros();
1673  EVT ShiftTy = DCI.isBeforeLegalize() ?
1675  EVT CmpTy = N0.getValueType();
1676  SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1677  DAG.getConstant(ShiftBits, ShiftTy));
1678  SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
1679  return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1680  }
1681  }
1682  } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1683  Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1684  bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1685  // X < 0x100000000 -> (X >> 32) < 1
1686  // X >= 0x100000000 -> (X >> 32) >= 1
1687  // X <= 0x0ffffffff -> (X >> 32) < 1
1688  // X > 0x0ffffffff -> (X >> 32) >= 1
1689  unsigned ShiftBits;
1690  APInt NewC = C1;
1691  ISD::CondCode NewCond = Cond;
1692  if (AdjOne) {
1693  ShiftBits = C1.countTrailingOnes();
1694  NewC = NewC + 1;
1695  NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1696  } else {
1697  ShiftBits = C1.countTrailingZeros();
1698  }
1699  NewC = NewC.lshr(ShiftBits);
1700  if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
1701  EVT ShiftTy = DCI.isBeforeLegalize() ?
1703  EVT CmpTy = N0.getValueType();
1704  SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1705  DAG.getConstant(ShiftBits, ShiftTy));
1706  SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
1707  return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1708  }
1709  }
1710  }
1711  }
1712 
1713  if (isa<ConstantFPSDNode>(N0.getNode())) {
1714  // Constant fold or commute setcc.
1715  SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1716  if (O.getNode()) return O;
1717  } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1718  // If the RHS of an FP comparison is a constant, simplify it away in
1719  // some cases.
1720  if (CFP->getValueAPF().isNaN()) {
1721  // If an operand is known to be a nan, we can fold it.
1722  switch (ISD::getUnorderedFlavor(Cond)) {
1723  default: llvm_unreachable("Unknown flavor!");
1724  case 0: // Known false.
1725  return DAG.getConstant(0, VT);
1726  case 1: // Known true.
1727  return DAG.getConstant(1, VT);
1728  case 2: // Undefined.
1729  return DAG.getUNDEF(VT);
1730  }
1731  }
1732 
1733  // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1734  // constant if knowing that the operand is non-nan is enough. We prefer to
1735  // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1736  // materialize 0.0.
1737  if (Cond == ISD::SETO || Cond == ISD::SETUO)
1738  return DAG.getSetCC(dl, VT, N0, N0, Cond);
1739 
1740  // If the condition is not legal, see if we can find an equivalent one
1741  // which is legal.
1742  if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1743  // If the comparison was an awkward floating-point == or != and one of
1744  // the comparison operands is infinity or negative infinity, convert the
1745  // condition to a less-awkward <= or >=.
1746  if (CFP->getValueAPF().isInfinity()) {
1747  if (CFP->getValueAPF().isNegative()) {
1748  if (Cond == ISD::SETOEQ &&
1749  isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1750  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1751  if (Cond == ISD::SETUEQ &&
1752  isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1753  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1754  if (Cond == ISD::SETUNE &&
1755  isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1756  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1757  if (Cond == ISD::SETONE &&
1758  isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1759  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1760  } else {
1761  if (Cond == ISD::SETOEQ &&
1762  isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1763  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1764  if (Cond == ISD::SETUEQ &&
1765  isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1766  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1767  if (Cond == ISD::SETUNE &&
1768  isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1769  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1770  if (Cond == ISD::SETONE &&
1771  isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1772  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1773  }
1774  }
1775  }
1776  }
1777 
1778  if (N0 == N1) {
1779  // The sext(setcc()) => setcc() optimization relies on the appropriate
1780  // constant being emitted.
1781  uint64_t EqVal = 0;
1782  switch (getBooleanContents(N0.getValueType())) {
1785  EqVal = ISD::isTrueWhenEqual(Cond);
1786  break;
1788  EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1789  break;
1790  }
1791 
1792  // We can always fold X == X for integer setcc's.
1793  if (N0.getValueType().isInteger()) {
1794  return DAG.getConstant(EqVal, VT);
1795  }
1796  unsigned UOF = ISD::getUnorderedFlavor(Cond);
1797  if (UOF == 2) // FP operators that are undefined on NaNs.
1798  return DAG.getConstant(EqVal, VT);
1799  if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1800  return DAG.getConstant(EqVal, VT);
1801  // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1802  // if it is not already.
1803  ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1804  if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1805  getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1806  return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1807  }
1808 
1809  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1810  N0.getValueType().isInteger()) {
1811  if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1812  N0.getOpcode() == ISD::XOR) {
1813  // Simplify (X+Y) == (X+Z) --> Y == Z
1814  if (N0.getOpcode() == N1.getOpcode()) {
1815  if (N0.getOperand(0) == N1.getOperand(0))
1816  return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1817  if (N0.getOperand(1) == N1.getOperand(1))
1818  return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1819  if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1820  // If X op Y == Y op X, try other combinations.
1821  if (N0.getOperand(0) == N1.getOperand(1))
1822  return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1823  Cond);
1824  if (N0.getOperand(1) == N1.getOperand(0))
1825  return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1826  Cond);
1827  }
1828  }
1829 
1830  // If RHS is a legal immediate value for a compare instruction, we need
1831  // to be careful about increasing register pressure needlessly.
1832  bool LegalRHSImm = false;
1833 
1834  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1835  if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1836  // Turn (X+C1) == C2 --> X == C2-C1
1837  if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1838  return DAG.getSetCC(dl, VT, N0.getOperand(0),
1839  DAG.getConstant(RHSC->getAPIntValue()-
1840  LHSR->getAPIntValue(),
1841  N0.getValueType()), Cond);
1842  }
1843 
1844  // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1845  if (N0.getOpcode() == ISD::XOR)
1846  // If we know that all of the inverted bits are zero, don't bother
1847  // performing the inversion.
1848  if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1849  return
1850  DAG.getSetCC(dl, VT, N0.getOperand(0),
1851  DAG.getConstant(LHSR->getAPIntValue() ^
1852  RHSC->getAPIntValue(),
1853  N0.getValueType()),
1854  Cond);
1855  }
1856 
1857  // Turn (C1-X) == C2 --> X == C1-C2
1858  if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1859  if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1860  return
1861  DAG.getSetCC(dl, VT, N0.getOperand(1),
1862  DAG.getConstant(SUBC->getAPIntValue() -
1863  RHSC->getAPIntValue(),
1864  N0.getValueType()),
1865  Cond);
1866  }
1867  }
1868 
1869  // Could RHSC fold directly into a compare?
1870  if (RHSC->getValueType(0).getSizeInBits() <= 64)
1871  LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
1872  }
1873 
1874  // Simplify (X+Z) == X --> Z == 0
1875  // Don't do this if X is an immediate that can fold into a cmp
1876  // instruction and X+Z has other uses. It could be an induction variable
1877  // chain, and the transform would increase register pressure.
1878  if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1879  if (N0.getOperand(0) == N1)
1880  return DAG.getSetCC(dl, VT, N0.getOperand(1),
1881  DAG.getConstant(0, N0.getValueType()), Cond);
1882  if (N0.getOperand(1) == N1) {
1883  if (DAG.isCommutativeBinOp(N0.getOpcode()))
1884  return DAG.getSetCC(dl, VT, N0.getOperand(0),
1885  DAG.getConstant(0, N0.getValueType()), Cond);
1886  if (N0.getNode()->hasOneUse()) {
1887  assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1888  // (Z-X) == X --> Z == X<<1
1889  SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
1890  DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
1891  if (!DCI.isCalledByLegalizer())
1892  DCI.AddToWorklist(SH.getNode());
1893  return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1894  }
1895  }
1896  }
1897  }
1898 
1899  if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1900  N1.getOpcode() == ISD::XOR) {
1901  // Simplify X == (X+Z) --> Z == 0
1902  if (N1.getOperand(0) == N0)
1903  return DAG.getSetCC(dl, VT, N1.getOperand(1),
1904  DAG.getConstant(0, N1.getValueType()), Cond);
1905  if (N1.getOperand(1) == N0) {
1906  if (DAG.isCommutativeBinOp(N1.getOpcode()))
1907  return DAG.getSetCC(dl, VT, N1.getOperand(0),
1908  DAG.getConstant(0, N1.getValueType()), Cond);
1909  if (N1.getNode()->hasOneUse()) {
1910  assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1911  // X == (Z-X) --> X<<1 == Z
1912  SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1913  DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
1914  if (!DCI.isCalledByLegalizer())
1915  DCI.AddToWorklist(SH.getNode());
1916  return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1917  }
1918  }
1919  }
1920 
1921  // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1922  // Note that where y is variable and is known to have at most
1923  // one bit set (for example, if it is z&1) we cannot do this;
1924  // the expressions are not equivalent when y==0.
1925  if (N0.getOpcode() == ISD::AND)
1926  if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1927  if (ValueHasExactlyOneBitSet(N1, DAG)) {
1928  Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1929  if (DCI.isBeforeLegalizeOps() ||
1930  isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1931  SDValue Zero = DAG.getConstant(0, N1.getValueType());
1932  return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1933  }
1934  }
1935  }
1936  if (N1.getOpcode() == ISD::AND)
1937  if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1938  if (ValueHasExactlyOneBitSet(N0, DAG)) {
1939  Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1940  if (DCI.isBeforeLegalizeOps() ||
1941  isCondCodeLegal(Cond, N1.getSimpleValueType())) {
1942  SDValue Zero = DAG.getConstant(0, N0.getValueType());
1943  return DAG.getSetCC(dl, VT, N1, Zero, Cond);
1944  }
1945  }
1946  }
1947  }
1948 
1949  // Fold away ALL boolean setcc's.
1950  SDValue Temp;
1951  if (N0.getValueType() == MVT::i1 && foldBooleans) {
1952  switch (Cond) {
1953  default: llvm_unreachable("Unknown integer setcc!");
1954  case ISD::SETEQ: // X == Y -> ~(X^Y)
1955  Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1956  N0 = DAG.getNOT(dl, Temp, MVT::i1);
1957  if (!DCI.isCalledByLegalizer())
1958  DCI.AddToWorklist(Temp.getNode());
1959  break;
1960  case ISD::SETNE: // X != Y --> (X^Y)
1961  N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1962  break;
1963  case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
1964  case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
1965  Temp = DAG.getNOT(dl, N0, MVT::i1);
1966  N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1967  if (!DCI.isCalledByLegalizer())
1968  DCI.AddToWorklist(Temp.getNode());
1969  break;
1970  case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
1971  case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
1972  Temp = DAG.getNOT(dl, N1, MVT::i1);
1973  N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
1974  if (!DCI.isCalledByLegalizer())
1975  DCI.AddToWorklist(Temp.getNode());
1976  break;
1977  case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
1978  case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
1979  Temp = DAG.getNOT(dl, N0, MVT::i1);
1980  N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
1981  if (!DCI.isCalledByLegalizer())
1982  DCI.AddToWorklist(Temp.getNode());
1983  break;
1984  case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
1985  case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
1986  Temp = DAG.getNOT(dl, N1, MVT::i1);
1987  N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
1988  break;
1989  }
1990  if (VT != MVT::i1) {
1991  if (!DCI.isCalledByLegalizer())
1992  DCI.AddToWorklist(N0.getNode());
1993  // FIXME: If running after legalize, we probably can't do this.
1994  N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
1995  }
1996  return N0;
1997  }
1998 
1999  // Could not fold it.
2000  return SDValue();
2001 }
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
unsigned Log2_32_Ceil(uint32_t Value)
Definition: MathExtras.h:465
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:448
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
SDValue getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT, EVT OpVT)
bool hasOneUse() const
bool hasOneUse() const
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:526
bool isUnindexed() const
isUnindexed - Return true if this is NOT a pre/post inc/dec load/store.
virtual bool isLegalICmpImmediate(int64_t) const
unsigned getValueSizeInBits() const
const SDValue & getOperand(unsigned Num) const
static bool isCommutativeBinOp(unsigned Opcode)
bool isTrueWhenEqual(CondCode Cond)
Definition: ISDOpcodes.h:809
const SDValue & getBasePtr() const
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
Definition: APInt.h:421
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
Definition: ValueTypes.h:190
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
EVT getShiftAmountTy(EVT LHSTy) const
bool isLittleEndian() const
bool isRound() const
isRound - Return true if the size is a power-of-two number of bytes.
Definition: ValueTypes.h:166
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
EVT getValueType(unsigned ResNo) const
APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.cpp:1128
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const
MachinePointerInfo getWithOffset(int64_t O) const
virtual MVT getPointerTy(uint32_t=0) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDValue getUNDEF(EVT VT)
getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:625
EVT getMemoryVT() const
getMemoryVT - Return the type of the in-memory value.
bool isSignedIntSetCC(CondCode Code)
Definition: ISDOpcodes.h:796
bool bitsLE(EVT VT) const
bitsLE - Return true if this has no more bits than VT.
Definition: ValueTypes.h:196
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
SDNode * getNode() const
get the SDNode which holds the desired result
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG)
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1314
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
const DataLayout * getDataLayout() const
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1248
unsigned getOpcode() const
unsigned getUnorderedFlavor(CondCode Cond)
Definition: ISDOpcodes.h:817
CondCode getSetCCSwappedOperands(CondCode Operation)
bool isVolatile() const
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
const MachinePointerInfo & getPointerInfo() const
bool bitsGT(EVT VT) const
bitsGT - Return true if this has more bits than VT.
Definition: ValueTypes.h:178
unsigned countTrailingZeros() const
Count the number of trailing zero bits.
Definition: APInt.cpp:737
SDValue getNOT(SDLoc DL, SDValue Val, EVT VT)
getNOT - Create a bitwise NOT operation as (XOR Val, -1).
const SDValue & getChain() const
static APInt getMinValue(unsigned numBits)
Gets minimum unsigned value of APInt for a specific bit width.
Definition: APInt.h:428
CondCode getSetCCInverse(CondCode Operation, bool isInteger)
unsigned Log2_32(uint32_t Value)
Definition: MathExtras.h:452
ISD::LoadExtType getExtensionType() const
Class for arbitrary precision integers.
Definition: APInt.h:75
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
static APInt getMaxValue(unsigned numBits)
Gets maximum unsigned value of APInt for specific bit width.
Definition: APInt.h:416
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1865
uint64_t MinAlign(uint64_t A, uint64_t B)
Definition: MathExtras.h:544
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
unsigned countTrailingOnes() const
Count the number of trailing one bits.
Definition: APInt.h:1378
SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, SDLoc dl)
FoldSetCC - Constant fold a setcc to true or false.
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
Definition: APInt.h:431
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Definition: SelectionDAG.h:690
BooleanContent
Enum that describes how the target represents true/false values.
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
unsigned getAlignment() const
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Definition: ValueTypes.h:62
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
MVT getSimpleVT() const
Definition: ValueTypes.h:204
void TargetLowering::softenSetCCOperands ( SelectionDAG DAG,
EVT  VT,
SDValue NewLHS,
SDValue NewRHS,
ISD::CondCode CCCode,
SDLoc  dl 
) const
inherited

SoftenSetCCOperands - Soften the operands of a comparison. This code is shared among BR_CC, SELECT_CC, and SETCC handlers.

Definition at line 117 of file TargetLowering.cpp.

120  {
121  assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
122  && "Unsupported setcc type!");
123 
124  // Expand into one or more soft-fp libcall(s).
126  switch (CCCode) {
127  case ISD::SETEQ:
128  case ISD::SETOEQ:
129  LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
131  break;
132  case ISD::SETNE:
133  case ISD::SETUNE:
134  LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
136  break;
137  case ISD::SETGE:
138  case ISD::SETOGE:
139  LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
141  break;
142  case ISD::SETLT:
143  case ISD::SETOLT:
144  LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
146  break;
147  case ISD::SETLE:
148  case ISD::SETOLE:
149  LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
151  break;
152  case ISD::SETGT:
153  case ISD::SETOGT:
154  LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
156  break;
157  case ISD::SETUO:
158  LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
160  break;
161  case ISD::SETO:
162  LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
163  (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
164  break;
165  default:
166  LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
168  switch (CCCode) {
169  case ISD::SETONE:
170  // SETONE = SETOLT | SETOGT
171  LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
173  // Fallthrough
174  case ISD::SETUGT:
175  LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
177  break;
178  case ISD::SETUGE:
179  LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
181  break;
182  case ISD::SETULT:
183  LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
185  break;
186  case ISD::SETULE:
187  LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
189  break;
190  case ISD::SETUEQ:
191  LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
193  break;
194  default: llvm_unreachable("Do not know how to soften this setcc!");
195  }
196  }
197 
198  // Use the target specific return value for comparions lib calls.
199  EVT RetVT = getCmpLibcallReturnType();
200  SDValue Ops[2] = { NewLHS, NewRHS };
201  NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
202  dl).first;
203  NewRHS = DAG.getConstant(0, RetVT);
204  CCCode = getCmpLibcallCC(LC1);
205  if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
206  SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
207  getSetCCResultType(*DAG.getContext(), RetVT),
208  NewLHS, NewRHS, DAG.getCondCode(CCCode));
209  NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/,
210  dl).first;
211  NewLHS = DAG.getNode(ISD::SETCC, dl,
212  getSetCCResultType(*DAG.getContext(), RetVT), NewLHS,
213  NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
214  NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
215  NewRHS = SDValue();
216  }
217 }
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const
assert(Globals.size() > 1)
ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
EVT getValueType() const
SDValue getCondCode(ISD::CondCode Cond)
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
bool llvm::TargetLoweringBase::supportJumpTables ( ) const
inlineinherited

Return whether the target can generate code for jump tables.

Definition at line 827 of file TargetLowering.h.

827  {
828  return SupportJumpTables;
829  }
bool llvm::TargetLoweringBase::usesUnderscoreLongJmp ( ) const
inlineinherited

Determine if we should use _longjmp or longjmp to implement llvm.longjmp.

Definition at line 822 of file TargetLowering.h.

822  {
823  return UseUnderscoreLongJmp;
824  }
bool llvm::TargetLoweringBase::usesUnderscoreSetJmp ( ) const
inlineinherited

Determine if we should use _setjmp or setjmp to implement llvm.setjmp.

Definition at line 817 of file TargetLowering.h.

817  {
818  return UseUnderscoreSetJmp;
819  }
bool TargetLowering::verifyReturnAddressArgumentIsConstant ( SDValue  Op,
SelectionDAG DAG 
) const
inherited

Definition at line 2772 of file TargetLowering.cpp.

2772  {
2773  if (!isa<ConstantSDNode>(Op.getOperand(0))) {
2774  DAG.getContext()->emitError("argument to '__builtin_return_address' must "
2775  "be a constant integer");
2776  return true;
2777  }
2778 
2779  return false;
2780 }
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
void emitError(unsigned LocCookie, const Twine &ErrorStr)
const SDValue & getOperand(unsigned i) const

Field Documentation

bool llvm::TargetLoweringBase::MaskAndBranchFoldingIsLegal
protectedinherited

MaskAndBranchFoldingIsLegal - Indicates if the target supports folding a mask of a single bit, a compare, and a branch into a single instruction.

Definition at line 1842 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemcpy
protectedinherited

Specify maximum bytes of store instructions per memcpy call.

When lowering @llvm.memcpy this field specifies the maximum number of store operations that may be substituted for a call to memcpy. Targets must set this value based on the cost threshold for that target. Targets should assume that the memcpy will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 7 bytes on a 32-bit machine with 32-bit alignment would result in one 4-byte store, a one 2-byte store and one 1-byte store. This only applies to copying a constant array of constant size.

Definition at line 1814 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize
protectedinherited

Maximum number of store operations that may be substituted for a call to memcpy, used for functions with OptSize attribute.

Definition at line 1818 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemmove
protectedinherited

Specify maximum bytes of store instructions per memmove call.

When lowering @llvm.memmove this field specifies the maximum number of store instructions that may be substituted for a call to memmove. Targets must set this value based on the cost threshold for that target. Targets should assume that the memmove will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, moving 9 bytes on a 32-bit machine with 8-bit alignment would result in nine 1-byte stores. This only applies to copying a constant array of constant size.

Definition at line 1830 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize
protectedinherited

Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OpSize attribute.

Definition at line 1834 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemset
protectedinherited

Specify maximum number of store instructions per memset call.

When lowering @llvm.memset this field specifies the maximum number of store operations that may be substituted for the call to memset. Targets must set this value based on the cost threshold for that target. Targets should assume that the memset will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 9 bytes on a 32-bit machine with 16-bit alignment would result in four 2-byte stores and one 1-byte store. This only applies to setting a constant array of a constant size.

Definition at line 1797 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize
protectedinherited

Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.

Definition at line 1801 of file TargetLowering.h.

bool llvm::TargetLoweringBase::PredictableSelectIsExpensive
protectedinherited

Tells the code generator that select is more expensive than a branch if the branch is usually predicted right.

Definition at line 1838 of file TargetLowering.h.

bool llvm::AArch64TargetLowering::RequireStrictAlign
private

Definition at line 197 of file AArch64ISelLowering.h.

const AArch64Subtarget* llvm::AArch64TargetLowering::Subtarget
private

Subtarget - Keep a pointer to the AArch64Subtarget around so that we can make the right decision when generating code for different targets.

Definition at line 333 of file AArch64ISelLowering.h.


The documentation for this class was generated from the following files: